With water stacking, its not unreasonable to have high interconnect density for two different (highly optimized eg DRAM and FinFET) processes with high yield. I

With water stacking, its not unreasonable to have high interconnect density for two different (highly optimized eg DRAM and FinFET) processes with high yield. I expect it to happen sooner than later. Latency to extremely large caches could be significantly improved. I expect it to happen. https://semiengineering.com/whats-next-in-scaling-and-stacking/ https://semiengineering.com/whats-next-in-scaling-and-stacki...