> Register renaming, cache hierarchies, out of order and speculative execution etc are not visible at the assembly / machine code level Cache hierarchies are d

> Register renaming, cache hierarchies, out of order and speculative execution etc are not visible at the assembly / machine code level Cache hierarchies are directly accessible with CLFLUSH, INV, WBINVD x86 instructions; we may count also PREFETCHx, but they call it "a hint". FENCE instructions touch even the multicore part of system. Many low-level CPU concepts leak to higher layer. A bright example is false sharing, which may manifest even in Java or C# programs.