3 ms·
Whilst it's true that modern chips have problems with routing clocks, that's not really a limiting factor in chip size. You split the design into clock regions
by slivym 8y ago
Whilst it's true that modern chips have problems with routing clocks, that's not really a limiting factor in chip size. You split the design into clock regions and have clock crossing logic. There's obvious ways this happens - multi-core designs have different clocks for different cores for example. That's not really the limiting factor for chip size.
- Nokinside 8y agoThe cost of clock regions is slower speeds between tiles and more transistors and power wasted in clock management. In the end you need need buffers and cache for cache for cache to maintain speed and locality. All this wastes transistors.