3 ms·

Sure, as long as they bring current industry-standard QC processes to the party. I'm skeptical.

geezerjay 8y ago
If the price is right, there are plenty of applications where dodgy RAM is good enough. Once that starts to eat the incumbent's lunch the prices will follow.
- derefr 8y ago
  Are there CPU architectures/OSes/software frameworks built to deal with extremely flaky memory? Something like the Mars rovers' "six CPUs take a vote on what to do" architecture, but where those are just six NUMA nodes in the same workstation?
  - jotm 8y ago
    Somewhat related, I used several sets of unmarked DDR2 RAM (so I'm assuming either Chinese or factory rejects) back in the day, and it worked without problems for years. That was after a 24 hour run of Memtest, which I do for all new modules.
  - monocasa 8y ago
    I've heard on the grapevine that essentially all modern DRAM is dodgy and ECCs internally (sort of like flash). When you're buying ECC RAM, it's just exposing that on the bus for end to end ECC.
    - mehrdada 8y ago
      This sounds suspect (perhaps depending on what do you mean by modern?) I am curious if there's a reference?
      - monocasa 8y ago
        Grapevine being drinking with DRAM engineers. I don't know if there's a reference.
    - PhantomGremlin 8y ago
      If true, it's the "wheel of reincarnation" all over again. Back about 35 years ago, perhaps for the 256 kbit DRAM generation, IIRC it was Micron that did something like this. I tried some quick Googling and didn't find anything. But it's really hit and miss how much stuff that precedes the WWW can be turned up by a quick search. The Micron idea was that they would use a (12,8) Hamming type code. A total of 12 bits including 8 data bits. Which, if you recall the theory behind these codes, meant that you could do Single Error Correction, but not Double Error Detection (that would take a 13th bit). Not doing DED was a "feature", since these chips were pin compatible with standard memory. So you had no easy way to signal an error anyway. I don't think the product was very successful (if it ever made it into volume production) because of the incredible overhead it would take. Instead of 262144 total memory bits on the die, you needed 50% more, i.e. 393216. On the plus side, you could make each cell a little bit smaller, and you wouldn't really care about a few individual bad bits (those would be hidden by the ECC). So your yield probably went up. But of course the die was so much bigger, so your yield went way down because of that. Tradeoffs, tradeoffs, tradeoffs! Overall, if you were Micron I suppose you were just happy if the finished chip met some appropriate AQL standard. What it did on die was just an implementation detail. :)

If the price is right, there are plenty of applications where dodgy RAM is good enough. Once that starts to eat the incumbent's lunch the prices will follow.

derefr 8y ago
Are there CPU architectures/OSes/software frameworks built to deal with extremely flaky memory? Something like the Mars rovers' "six CPUs take a vote on what to do" architecture, but where those are just six NUMA nodes in the same workstation?
- jotm 8y ago
  Somewhat related, I used several sets of unmarked DDR2 RAM (so I'm assuming either Chinese or factory rejects) back in the day, and it worked without problems for years. That was after a 24 hour run of Memtest, which I do for all new modules.
- monocasa 8y ago
  I've heard on the grapevine that essentially all modern DRAM is dodgy and ECCs internally (sort of like flash). When you're buying ECC RAM, it's just exposing that on the bus for end to end ECC.
  - mehrdada 8y ago
    This sounds suspect (perhaps depending on what do you mean by modern?) I am curious if there's a reference?
    - monocasa 8y ago
      Grapevine being drinking with DRAM engineers. I don't know if there's a reference.
  - PhantomGremlin 8y ago
    If true, it's the "wheel of reincarnation" all over again. Back about 35 years ago, perhaps for the 256 kbit DRAM generation, IIRC it was Micron that did something like this. I tried some quick Googling and didn't find anything. But it's really hit and miss how much stuff that precedes the WWW can be turned up by a quick search. The Micron idea was that they would use a (12,8) Hamming type code. A total of 12 bits including 8 data bits. Which, if you recall the theory behind these codes, meant that you could do Single Error Correction, but not Double Error Detection (that would take a 13th bit). Not doing DED was a "feature", since these chips were pin compatible with standard memory. So you had no easy way to signal an error anyway. I don't think the product was very successful (if it ever made it into volume production) because of the incredible overhead it would take. Instead of 262144 total memory bits on the die, you needed 50% more, i.e. 393216. On the plus side, you could make each cell a little bit smaller, and you wouldn't really care about a few individual bad bits (those would be hidden by the ECC). So your yield probably went up. But of course the die was so much bigger, so your yield went way down because of that. Tradeoffs, tradeoffs, tradeoffs! Overall, if you were Micron I suppose you were just happy if the finished chip met some appropriate AQL standard. What it did on die was just an implementation detail. :)