3 ms·
I'm not sure of the methods, but it's documented that invariant TSC is constant. Operating systems depend on that if the CPUID feature bit is set. https://soft
by notaplumber 8y ago
I'm not sure of the methods, but it's documented that invariant TSC is constant. Operating systems depend on that if the CPUID feature bit is set.
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf https://software.intel.com/sites/default/files/managed/39/c5... (24MB mobile warning):
"17.17.1 Invariant TSC"
"The invariant TSC will run at a constant rate in all ACPI P-, C-, and T-states. This is an architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition [system call, u<=>k context switch] or access to a platform resource. [Device I/O]"
If overclockers methods are breaking this promise, then operating systems have very little recourse. I suspect they are not, however. The point is that the TSC is not derived from the CPU clock.
- wtallis 8y ago> If overclockers methods are breaking this promise, then operating systems have very little recourse. I guess the real concern is where does software get its information about the ratio of the TSC's rate to the progression of actual wall time. If it's derived from a constant multiplier of the CPU base clock or something like that, then adjusting the base clock could be quite problematic for benchmarking even if that base clock speed remains constant throughout a benchmark run. On the other hand, if the TSC to wall time ratio is measured using an external clock (like HPET), then most overclocking situations are probably fine (since it's pretty rare to overclock peripheral busses on modern platforms). And since RDTSC is quite deliberately an unprivileged instruction, it's not just the OS we have to worry about on the software side. But hopefully most application authors that directly use the TSC instead of portable APIs know what they're doing. (I wouldn't bet on it.)
- notaplumber 8y agoThe TSC is periodically recalibrated by operating systems from the some other available timer, like HPET or ACPI PM timer.
- dragontamer 8y agoExtreme overclockers on Intel platforms DO change the BCLK, which from my understanding, changes the TSC timing. https://www.tweaktown.com/guides/7481/tweaktowns-ultimate-intel-skylake-overclocking-guide/index3.html https://www.tweaktown.com/guides/7481/tweaktowns-ultimate-in... Its not a "common" practice, but its certainly an overclocking practice that enough overclockers do that its a concern.