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This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep

This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI https://www.youtube.com/watch?v=5yTARacBxHI - it's both fascinating and terrifying the trouble that EUV brings) and mirrors since pretty much all matter is opaque to EUV light. It's a bit maddening to think that features that much smaller than the wavelength of light used can be patterned with that light source, but we've made a science out of it over the past decade with multipatterning and immersion lithography.

CamperBob2 9y ago
So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength? I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.
- kurthr 9y ago
  It's worse than that... there's not jist an industry group (ITRS), there's also the foundries making it up themselves. They're buying similar equipment and selling similar transistor densities (except for Intel which has finer geometries and higher densities for a given node), but few are directly compatible on density, clock-rate, or power consumption after 28nm. https://en.m.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductors https://en.m.wikipedia.org/wiki/International_Technology_Roa... Scalling really started falling apart in the late 90s around .25u, and then (incidentally) about the time CPU MHZ stopped scaling... by 65nm both gate and transistor length got wonky. Then after 28nm they moved to fin-FETs and multi-patterning making comparisons even more difficult. https://semiengineering.com/a-node-by-any-other-name/ https://semiengineering.com/a-node-by-any-other-name/
- awalton 9y ago
  It used to be a specific feature size: the length of the gate. But, even as the wheels came off of that pretty quickly, the convention stayed pretty simple and familiar: each process node halves the size of the one before it - you can print double the number of transistors at the smaller process node. To make the math work out, that means each process node "name" is sqrt(1/2) ~= 0.7x smaller than the last, which gives you the easy-to-follow node names from 3um to about 3nm (when people tend to switch to ångströms or picometers since it moves the decimal kindly). Even as things got sticky due to advancements in transistor construction meaning that old metrics like gate length were obsolete, we were still roughly following the trend laid out ahead of us for decades. A new process would double your density, letting you roughly cut the size of your old chip in half. ...Until a few fab companies just up and decided "You know what, fuck it, we can't actually catch up to Intel, but if what if we just... say that we did?" (...and I wish I was kidding. Take a look: https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jpg https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jp... vs https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jpg https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jp...). So pretty quickly, TSMC decided that they'd just advance the node table, despite not actually increasing the density by double as you'd expect. "Next generation" 20nm processes became "16nm" and "14nm" on marketing docs, despite the process capabilities not changing that much (or even at all in some cases), with the only thing close to a justification given is that "FinFETs are different. They perform better than planar FETs so we should be able to give them a new node name." GloFo and Samsung quickly took the bit and followed their lead as they began FinFET manufacturing. And apparently since nobody blinked an eye or set off alarm bells about these fabs basically lying about their capabilities, they got away with it and are now continuing the trend downwards. "10nm" processes from TSMC, Samsung and GloFo measure up to Intel's 14nm, and now "7nm" processes measure up to Intel's 10nm. It's actually pretty surprising Intel hasn't thrown up its hands and joined them on the fun, or even come up with their own marketing spin on it yet. "Intel's new 7nm-xtreme manufacturing process (actually it's just 10nm+)" or whatever.
  - kingosticks 9y ago
    Who exactly would be responding to these alarm bells? If I'm making a chip I want to use the node that best fits my product. Might not even be the latest one. But if they offer me 2x the memory destiny, 1.6x the logic density all at the same/lower power - I'll take it! Sure, the tracks are huge and I need a huge tall stack-up but that's not really my problem. I really don't care what marketing speak they use to refer to it. I have zero interest how long the gate is, I care about what chip I can make with this. And Intel can do what they want. Their fab offering is very uncompetitive.
baybal2 9y ago
>- it's both fascinating and terrifying the trouble that EUV brings It is only peanuts in comparison to what is to come. The "nuclear option" on the table is to build a whole fab around a freaking synchrotron light source.
- CamperBob2 9y ago
  I watched the video recommended by awalton, and it's definitely as insane as he says it is. I can't believe a synchrotron would be that much more expensive, considering that a single storage ring can have an arbitrary number of output ports.
  - Nanite 9y ago
    The main issue with using a synchrotron or Free Electron Laser EUV source might not be so much about the technology, but more about the mindset of the clients (Samsung, TSMC, Global Foundries, Intel). Up until now lithography has been something they would buy as a "box" which would be shipped to their fab, "plugged in" and commissioned. A Free Electron Laser EUV source would be a facility on it's own, similar in size to a small powerplant built adjacent to your fab, and multiplexed to a dozen or so EUV wafer scanners, that's quite a different endeavor.
    - baybal2 9y ago
      And after that, and few EUV multiple patterning litho generation, lies a pitch black abyss called Deep X-Ray Lithography, the only thing that can push things closer to 1nm
JoachimS 9y ago
"but we've made a science out of it" Not just science, but working, high volume, commercially viable production processes. The science itself is extremely impressive, but then adding commercial requirements and pull it off. Over and over again.
JoachimS 9y ago
Great movie. Those machines are monsters. A 2m high machine that sits inside the ASML machine. And is fed laser light from something like a shipping container in the basement.
JoachimS 9y ago
Imaging presenting the idea for that light source. "How about letting droplets of molten tin fall through a vacuum and then blast it with CO2 lasers." BTW: The light must be blinking, right? In time with the frequency of the droplets.
beautifulfreak 9y ago
He says they hope to do 100 wafers per hour. I wonder how many dies will be on a wafer.
- exDM69 9y ago
  With current technology, a wafer is 10" in diameter (254mm), the aperture size limiting the die size is around 900 mm^2, so a chip is at most about 30x30mm. This would make it about 60-70 chips per wafer at maximum chip size (e.g. high end GPU). Most chips are a lot smaller, but there's a ballpark figure for you. Chips are square but wafers are round, so there's a lot more wasted area with large chips.

CamperBob2 9y ago

So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength? I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.

kurthr 9y ago
It's worse than that... there's not jist an industry group (ITRS), there's also the foundries making it up themselves. They're buying similar equipment and selling similar transistor densities (except for Intel which has finer geometries and higher densities for a given node), but few are directly compatible on density, clock-rate, or power consumption after 28nm. https://en.m.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductors https://en.m.wikipedia.org/wiki/International_Technology_Roa... Scalling really started falling apart in the late 90s around .25u, and then (incidentally) about the time CPU MHZ stopped scaling... by 65nm both gate and transistor length got wonky. Then after 28nm they moved to fin-FETs and multi-patterning making comparisons even more difficult. https://semiengineering.com/a-node-by-any-other-name/ https://semiengineering.com/a-node-by-any-other-name/
awalton 9y ago
It used to be a specific feature size: the length of the gate. But, even as the wheels came off of that pretty quickly, the convention stayed pretty simple and familiar: each process node halves the size of the one before it - you can print double the number of transistors at the smaller process node. To make the math work out, that means each process node "name" is sqrt(1/2) ~= 0.7x smaller than the last, which gives you the easy-to-follow node names from 3um to about 3nm (when people tend to switch to ångströms or picometers since it moves the decimal kindly). Even as things got sticky due to advancements in transistor construction meaning that old metrics like gate length were obsolete, we were still roughly following the trend laid out ahead of us for decades. A new process would double your density, letting you roughly cut the size of your old chip in half. ...Until a few fab companies just up and decided "You know what, fuck it, we can't actually catch up to Intel, but if what if we just... say that we did?" (...and I wish I was kidding. Take a look: https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jpg https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jp... vs https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jpg https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jp...). So pretty quickly, TSMC decided that they'd just advance the node table, despite not actually increasing the density by double as you'd expect. "Next generation" 20nm processes became "16nm" and "14nm" on marketing docs, despite the process capabilities not changing that much (or even at all in some cases), with the only thing close to a justification given is that "FinFETs are different. They perform better than planar FETs so we should be able to give them a new node name." GloFo and Samsung quickly took the bit and followed their lead as they began FinFET manufacturing. And apparently since nobody blinked an eye or set off alarm bells about these fabs basically lying about their capabilities, they got away with it and are now continuing the trend downwards. "10nm" processes from TSMC, Samsung and GloFo measure up to Intel's 14nm, and now "7nm" processes measure up to Intel's 10nm. It's actually pretty surprising Intel hasn't thrown up its hands and joined them on the fun, or even come up with their own marketing spin on it yet. "Intel's new 7nm-xtreme manufacturing process (actually it's just 10nm+)" or whatever.
- kingosticks 9y ago
  Who exactly would be responding to these alarm bells? If I'm making a chip I want to use the node that best fits my product. Might not even be the latest one. But if they offer me 2x the memory destiny, 1.6x the logic density all at the same/lower power - I'll take it! Sure, the tracks are huge and I need a huge tall stack-up but that's not really my problem. I really don't care what marketing speak they use to refer to it. I have zero interest how long the gate is, I care about what chip I can make with this. And Intel can do what they want. Their fab offering is very uncompetitive.

baybal2 9y ago

>- it's both fascinating and terrifying the trouble that EUV brings It is only peanuts in comparison to what is to come. The "nuclear option" on the table is to build a whole fab around a freaking synchrotron light source.

CamperBob2 9y ago
I watched the video recommended by awalton, and it's definitely as insane as he says it is. I can't believe a synchrotron would be that much more expensive, considering that a single storage ring can have an arbitrary number of output ports.
- Nanite 9y ago
  The main issue with using a synchrotron or Free Electron Laser EUV source might not be so much about the technology, but more about the mindset of the clients (Samsung, TSMC, Global Foundries, Intel). Up until now lithography has been something they would buy as a "box" which would be shipped to their fab, "plugged in" and commissioned. A Free Electron Laser EUV source would be a facility on it's own, similar in size to a small powerplant built adjacent to your fab, and multiplexed to a dozen or so EUV wafer scanners, that's quite a different endeavor.
  - baybal2 9y ago
    And after that, and few EUV multiple patterning litho generation, lies a pitch black abyss called Deep X-Ray Lithography, the only thing that can push things closer to 1nm

JoachimS 9y ago

"but we've made a science out of it" Not just science, but working, high volume, commercially viable production processes. The science itself is extremely impressive, but then adding commercial requirements and pull it off. Over and over again.

JoachimS 9y ago

Great movie. Those machines are monsters. A 2m high machine that sits inside the ASML machine. And is fed laser light from something like a shipping container in the basement.

JoachimS 9y ago

Imaging presenting the idea for that light source. "How about letting droplets of molten tin fall through a vacuum and then blast it with CO2 lasers." BTW: The light must be blinking, right? In time with the frequency of the droplets.

beautifulfreak 9y ago

He says they hope to do 100 wafers per hour. I wonder how many dies will be on a wafer.

exDM69 9y ago
With current technology, a wafer is 10" in diameter (254mm), the aperture size limiting the die size is around 900 mm^2, so a chip is at most about 30x30mm. This would make it about 60-70 chips per wafer at maximum chip size (e.g. high end GPU). Most chips are a lot smaller, but there's a ballpark figure for you. Chips are square but wafers are round, so there's a lot more wasted area with large chips.