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>"There are three major processor architectures: register, stack, and accumulator. In a register architecture, operations such as addition or subtraction can oc

>"There are three major processor architectures: register, stack, and accumulator. In a register architecture, operations such as addition or subtraction can occur between any two arbitrary registers. In a stack architecture, operations occur between the top of the stack and other items on the stack. In an accumulator architecture, the processor has single calculation register called the accumulator." I have only ever seen register and stack used to distinguish between a virtual machine implementation - i.e a "stack machine", example - the JVM , a "register machine", example - Dalvik. The author explains that the x86 is register based architecture but what are some examples of a stack based CPU architecture and an accumulator based CPU architecture?

shagie 9y ago
The 6502 and many of its kindred are accumulator based machines. From http://nesdev.com/6502.txt http://nesdev.com/6502.txt > THE ACCUMULATOR > This is THE most important register in the microprocessor. Various machine language instructions allow you to copy the contents of a memory location into the accumulator, copy the contents of the accumulator into a memory location, modify the contents of the accumulator or some other register directly, without affecting any memory. And the accumulator is the only register that has instructions for performing math. It has some other registers (X, Y, Status, Program Counter and Stack Pointer). Looking at the instruction set ( http://www.e-tradition.net/bytes/6502/6502_instruction_set.html http://www.e-tradition.net/bytes/6502/6502_instruction_set.h... ) , you'll see that all of the math operands work off of the accumulator. X and Y are primarily for the offset for a memory location.
- bogomipz 9y ago
  Thanks, architectures where the accumulator is always used implicitly then? I have often heard "register based architecture" used to describe MIPS/load store type architectures. It seems that the author here is implying that the x86 is "register based" since they''re stating its not actually an "accumulator machine" does have an accumulator like register?
  - pvg 9y ago
    The terms aren't super-formally defined but "register based" usually suggests "has a bunch of general purpose registers", load store doesn't have to be a part of it. A 68k has a bunch of general purpose(ish) registers.
  - pjc50 9y ago
    The PIC16 is probably the closest - all arithmetic has to go through the W register. Confusingly PIC calls all internal memory "registers", but really it's more like a one-register machine. The Z80 routes most arithmetic through its A (accumulator) register. The inheritor of this is the X86, where there are much fewer register limitations but tradition and the lettering remain; (E)AX is the calling convention's first argument and return parameter. And the article itself details that you can get shorter opcodes by preferring to do arithmetic through EAX.
  - shagie 9y ago
    In 6502, there is LDA, LDX, LDY for various loads. However, ADC (add with carry) only works on the accumulator. Another important aspect of (at least the 6502) is a very limited instruction set. With addressing modes and op codes there are at most 256 of them (one byte). ADC with addressing modes is 8 of the 256 instructions. AND (bitwise and memory location with accumulator) is another 8. And so on. To add the corresponding op codes for the X and Y registers - beyond adding more transistors - adds more op codes which were also at a premium. Granted, there are 105 of the 256 that weren’t used, but to make the 6502 into a design that would more closely match a three register architecture rather than an accumulator architecture would significantly eat into the unused op codes. Hypothetical ADCX and ADCY would be 12 or 16 more op codes. Eight more opcodes with that fully support the X and Y registers would consume all of those potential instructions (only six more opcodes if the accumulator is allowable as an offset).
  - pwg 9y ago
    The definitions are not strict, and there is often significant overlap between the categorization types (esp. as follow-on additions are added to the initial designs). But generally, things fall out this way: 1) register based Has a pool of registers, and the registers are general purpose (meaning they can be used as source or destination for most any computation operation the CPU can perform). 2) accumulator based Has a "dignified" register (the accumulator) and most computations only happen in/out of the accumulator. Other registers exist for more specialized purposes to facilitate feeding data into and out of the accumulator. Many DSP architectures are very highly "accumulator based". General purpose CPU's, less so unless you go back in time to late 70's or early 80's architectures. 3) stack based Has no registers (or very few) other than a stack pointer. All temporary data is stored on the stack, and all computation instructions involve computing with data items at the top of the stack and returning the result to the top of the stack. An example of such an architecture was the HP3000 system from the 70's (https://en.wikipedia.org/wiki/HP_3000#Use_of_stack_instead_of_registers https://en.wikipedia.org/wiki/HP_3000#Use_of_stack_instead_o...).
amluto 9y ago
Knuth’s MIX. Z80 is also sort-of an accumulator architecture, to a greater extent than x86.
pvg 9y ago
One way you can look at 'accumulator architecture' is as a special, constrained case of 'register machine' that makes sense when you're making CPUs out of 3510 transistors. A modern virtual machine and the CPUs it would target have grown past the constraint so you don't see that particular approach any more.
- bogomipz 9y ago
  Sorry can you explain why it only makes sense when your making cpus out of 3510 transistor? What constraint specifically are you referring to? Thanks.
  - pvg 9y ago
    Registers are part of the CPU so they take up room and transistors - when those things are at a premium, you use fewer registers. Then Moore's law magically lets you use more so you do!
    - caf 9y ago
      It's not so much the registers themselves, it's the plumbing required if you're going to let any register supply any input or output of the ALU. Hardwiring a register to one of the ALU's ports means you avoid a multiplexer (and the same applies to hardwiring a register to the AGU's ports, which is how you get 'base' and 'index' type registers).
      - pvg 9y ago
        Sure, there are lots and lots of deeper details but fundamentally, more registers means more transistors (or a higher-level logical unit of choice) and it's the constraint that drives accumulator-centric designs, specialized registers, etc. Relax the constraint and they become less necessary.
  - PhantomGremlin 9y ago
    Others have mentioned various reasons. Here's yet another reason: Shorter instructions. Let's say you have an 8-bit machine, like a 6502 or an 8080 (the architectural predecessor to the x86). Let's say everything goes thru the ACCumulator. Then you can have 1 byte opcodes to do things such as: clear accumulator shift left everything in ACC by 1 bit rotate left everything in ACC by 1 bit etc. You can also have 2 byte opcodes to do things such as: add an 8 bit immediate to the ACC 8 bit opcode plus 8 bit data exclusive or an 8 bit immediate to the ACC 8 bit opcode plus 8 bit data etc. Those early microprocessors used a lot of 8 bit and 16 bit instructions. Why? Cost and chip count. Early EPROMs (equivalent of today's flash but could only be erased by shining UV light on them), like the Intel 1702A, were 256 bytes. That's it. 2048 bits of memory in a chip. It was great when the Intel 2708 became reasonably priced. That got you an entire 1024 bytes of ROM in a single chip. Early RAMs, like the 2102, were 1024 words by 1 bit. Put 8 chips together and you got 1024 bytes of memory. So, yeah, shorter instructions were a big big deal in "the old days", i.e. the mid 1970s.
innocenat 9y ago
For stack machine, RTX2010 comes to mind. It's a radiation-hardened processor used in various spaceships.
- gh02t 9y ago
  Neat, I didn't know about this chip. Is there anything particular about a stack architecture that makes it ideal for radhard applications, or is it just the one they selected because they wanted to use Forth?
  - my123 9y ago
    It's mostly about convenience. Hubble uses a radiation hardened 486 instead of those.
- kabdib 9y ago
  Also, the INMOS Transputer. It's a seriously odd but inspired architecture. Didn't scale in performance. Had some really interesting ideas in its ISA and interprocessor communication system.
userbinator 9y ago
Most of the early computers were accumulator-based; and the concept predates computers, since the early mechanical calculators had a single "register" --- the accumulator --- which... accumulated the results of successive calculation. It's no surprise that computers, which initially were developed to be essentially automatic calculators, adopted the same architecture: https://en.wikipedia.org/wiki/Arithmometer https://en.wikipedia.org/wiki/Arithmometer https://en.wikipedia.org/wiki/Comptometer https://en.wikipedia.org/wiki/Comptometer
- adrianratnapala 9y ago
  I suspect it was also rational, given the performance trade-offs at the time. As transistors have become smaller, the caching hierarchy has become more important. A modern register set is a level-0 cache -- i.e. a useful pool of memory that is really close to the the computation units. In the old days, the communication between components was less of a bottleneck than the speed of the components themselves. So there was less advantage to this. On the other hand, making a CPU simpler by having just one or two registers was more of an advantage than it is now.
skissane 9y ago
The original CISC HP 3000s were a stack machine. Newer HP 3000s used PA-RISC CPUs instead (register not stack CPU), but the MPE operating system included an emulator/translator so they could still run the legacy CISC code. (The same architecture was also used in some of the early HP 9000 workstations, specifically the 500 series.)
- skissane 9y ago
  Another example of stack machines was the original Tandem architecture, which was based on HP 3000. (Most of the early Tandem team had come from HP.) Tandem then moved away from stack machines, to MIPS – but like the HP-3000 RISC transition, the MIPS Tandems had an emulator/translator for the original stack machine architecture. From MIPS, Tandem moved to Itanium, and now to x86. And, having been founded by ex-HP engineers, Tandem is now part of HPE.
abfan1127 9y ago
isn't the Microchip Pic an Accumulator based architecture?
- monocasa 9y ago
  Yeah, those are basically fancier clones of a PDP-8.
zokier 9y ago
I think F18A architecture (used in GA144 chips) is stack based, optimized for running forth http://www.greenarraychips.com/home/documents/index.html#architecture http://www.greenarraychips.com/home/documents/index.html#arc...
Lionsion 9y ago
> what are some examples of a stack based CPU architecture https://en.wikipedia.org/wiki/Burroughs_large_systems https://en.wikipedia.org/wiki/Burroughs_large_systems

shagie 9y ago

The 6502 and many of its kindred are accumulator based machines. From http://nesdev.com/6502.txt http://nesdev.com/6502.txt > THE ACCUMULATOR > This is THE most important register in the microprocessor. Various machine language instructions allow you to copy the contents of a memory location into the accumulator, copy the contents of the accumulator into a memory location, modify the contents of the accumulator or some other register directly, without affecting any memory. And the accumulator is the only register that has instructions for performing math. It has some other registers (X, Y, Status, Program Counter and Stack Pointer). Looking at the instruction set ( http://www.e-tradition.net/bytes/6502/6502_instruction_set.html http://www.e-tradition.net/bytes/6502/6502_instruction_set.h... ) , you'll see that all of the math operands work off of the accumulator. X and Y are primarily for the offset for a memory location.

bogomipz 9y ago
Thanks, architectures where the accumulator is always used implicitly then? I have often heard "register based architecture" used to describe MIPS/load store type architectures. It seems that the author here is implying that the x86 is "register based" since they''re stating its not actually an "accumulator machine" does have an accumulator like register?
- pvg 9y ago
  The terms aren't super-formally defined but "register based" usually suggests "has a bunch of general purpose registers", load store doesn't have to be a part of it. A 68k has a bunch of general purpose(ish) registers.
- pjc50 9y ago
  The PIC16 is probably the closest - all arithmetic has to go through the W register. Confusingly PIC calls all internal memory "registers", but really it's more like a one-register machine. The Z80 routes most arithmetic through its A (accumulator) register. The inheritor of this is the X86, where there are much fewer register limitations but tradition and the lettering remain; (E)AX is the calling convention's first argument and return parameter. And the article itself details that you can get shorter opcodes by preferring to do arithmetic through EAX.
- shagie 9y ago
  In 6502, there is LDA, LDX, LDY for various loads. However, ADC (add with carry) only works on the accumulator. Another important aspect of (at least the 6502) is a very limited instruction set. With addressing modes and op codes there are at most 256 of them (one byte). ADC with addressing modes is 8 of the 256 instructions. AND (bitwise and memory location with accumulator) is another 8. And so on. To add the corresponding op codes for the X and Y registers - beyond adding more transistors - adds more op codes which were also at a premium. Granted, there are 105 of the 256 that weren’t used, but to make the 6502 into a design that would more closely match a three register architecture rather than an accumulator architecture would significantly eat into the unused op codes. Hypothetical ADCX and ADCY would be 12 or 16 more op codes. Eight more opcodes with that fully support the X and Y registers would consume all of those potential instructions (only six more opcodes if the accumulator is allowable as an offset).
- pwg 9y ago
  The definitions are not strict, and there is often significant overlap between the categorization types (esp. as follow-on additions are added to the initial designs). But generally, things fall out this way: 1) register based Has a pool of registers, and the registers are general purpose (meaning they can be used as source or destination for most any computation operation the CPU can perform). 2) accumulator based Has a "dignified" register (the accumulator) and most computations only happen in/out of the accumulator. Other registers exist for more specialized purposes to facilitate feeding data into and out of the accumulator. Many DSP architectures are very highly "accumulator based". General purpose CPU's, less so unless you go back in time to late 70's or early 80's architectures. 3) stack based Has no registers (or very few) other than a stack pointer. All temporary data is stored on the stack, and all computation instructions involve computing with data items at the top of the stack and returning the result to the top of the stack. An example of such an architecture was the HP3000 system from the 70's (https://en.wikipedia.org/wiki/HP_3000#Use_of_stack_instead_of_registers https://en.wikipedia.org/wiki/HP_3000#Use_of_stack_instead_o...).

amluto 9y ago

Knuth’s MIX. Z80 is also sort-of an accumulator architecture, to a greater extent than x86.

pvg 9y ago

One way you can look at 'accumulator architecture' is as a special, constrained case of 'register machine' that makes sense when you're making CPUs out of 3510 transistors. A modern virtual machine and the CPUs it would target have grown past the constraint so you don't see that particular approach any more.

bogomipz 9y ago
Sorry can you explain why it only makes sense when your making cpus out of 3510 transistor? What constraint specifically are you referring to? Thanks.
- pvg 9y ago
  Registers are part of the CPU so they take up room and transistors - when those things are at a premium, you use fewer registers. Then Moore's law magically lets you use more so you do!
  - caf 9y ago
    It's not so much the registers themselves, it's the plumbing required if you're going to let any register supply any input or output of the ALU. Hardwiring a register to one of the ALU's ports means you avoid a multiplexer (and the same applies to hardwiring a register to the AGU's ports, which is how you get 'base' and 'index' type registers).
    - pvg 9y ago
      Sure, there are lots and lots of deeper details but fundamentally, more registers means more transistors (or a higher-level logical unit of choice) and it's the constraint that drives accumulator-centric designs, specialized registers, etc. Relax the constraint and they become less necessary.
- PhantomGremlin 9y ago
  Others have mentioned various reasons. Here's yet another reason: Shorter instructions. Let's say you have an 8-bit machine, like a 6502 or an 8080 (the architectural predecessor to the x86). Let's say everything goes thru the ACCumulator. Then you can have 1 byte opcodes to do things such as: clear accumulator shift left everything in ACC by 1 bit rotate left everything in ACC by 1 bit etc. You can also have 2 byte opcodes to do things such as: add an 8 bit immediate to the ACC 8 bit opcode plus 8 bit data exclusive or an 8 bit immediate to the ACC 8 bit opcode plus 8 bit data etc. Those early microprocessors used a lot of 8 bit and 16 bit instructions. Why? Cost and chip count. Early EPROMs (equivalent of today's flash but could only be erased by shining UV light on them), like the Intel 1702A, were 256 bytes. That's it. 2048 bits of memory in a chip. It was great when the Intel 2708 became reasonably priced. That got you an entire 1024 bytes of ROM in a single chip. Early RAMs, like the 2102, were 1024 words by 1 bit. Put 8 chips together and you got 1024 bytes of memory. So, yeah, shorter instructions were a big big deal in "the old days", i.e. the mid 1970s.

innocenat 9y ago

For stack machine, RTX2010 comes to mind. It's a radiation-hardened processor used in various spaceships.

gh02t 9y ago
Neat, I didn't know about this chip. Is there anything particular about a stack architecture that makes it ideal for radhard applications, or is it just the one they selected because they wanted to use Forth?
- my123 9y ago
  It's mostly about convenience. Hubble uses a radiation hardened 486 instead of those.
kabdib 9y ago
Also, the INMOS Transputer. It's a seriously odd but inspired architecture. Didn't scale in performance. Had some really interesting ideas in its ISA and interprocessor communication system.

userbinator 9y ago

Most of the early computers were accumulator-based; and the concept predates computers, since the early mechanical calculators had a single "register" --- the accumulator --- which... accumulated the results of successive calculation. It's no surprise that computers, which initially were developed to be essentially automatic calculators, adopted the same architecture: https://en.wikipedia.org/wiki/Arithmometer https://en.wikipedia.org/wiki/Arithmometer https://en.wikipedia.org/wiki/Comptometer https://en.wikipedia.org/wiki/Comptometer

adrianratnapala 9y ago
I suspect it was also rational, given the performance trade-offs at the time. As transistors have become smaller, the caching hierarchy has become more important. A modern register set is a level-0 cache -- i.e. a useful pool of memory that is really close to the the computation units. In the old days, the communication between components was less of a bottleneck than the speed of the components themselves. So there was less advantage to this. On the other hand, making a CPU simpler by having just one or two registers was more of an advantage than it is now.

skissane 9y ago

The original CISC HP 3000s were a stack machine. Newer HP 3000s used PA-RISC CPUs instead (register not stack CPU), but the MPE operating system included an emulator/translator so they could still run the legacy CISC code. (The same architecture was also used in some of the early HP 9000 workstations, specifically the 500 series.)

skissane 9y ago
Another example of stack machines was the original Tandem architecture, which was based on HP 3000. (Most of the early Tandem team had come from HP.) Tandem then moved away from stack machines, to MIPS – but like the HP-3000 RISC transition, the MIPS Tandems had an emulator/translator for the original stack machine architecture. From MIPS, Tandem moved to Itanium, and now to x86. And, having been founded by ex-HP engineers, Tandem is now part of HPE.

abfan1127 9y ago

isn't the Microchip Pic an Accumulator based architecture?

monocasa 9y ago
Yeah, those are basically fancier clones of a PDP-8.

zokier 9y ago

I think F18A architecture (used in GA144 chips) is stack based, optimized for running forth http://www.greenarraychips.com/home/documents/index.html#architecture http://www.greenarraychips.com/home/documents/index.html#arc...

Lionsion 9y ago

> what are some examples of a stack based CPU architecture https://en.wikipedia.org/wiki/Burroughs_large_systems https://en.wikipedia.org/wiki/Burroughs_large_systems