I went to a talk from the CTO of Graphcore (https://www.graphcore.ai/ https://www.graphcore.ai/) on Monday. They are designing chips targeted at machine learni

I went to a talk from the CTO of Graphcore (https://www.graphcore.ai/ https://www.graphcore.ai/) on Monday. They are designing chips targeted at machine learning. As I understood it, their architecture comprises - lots of "tiles" - small processing cores with collocated memory (essentially DSPs) - very high bandwidth (90TB/s!) switching fabric to move data between tiles - "Bulk Synchronous Parallel" operation, meaning that the tiles do their work and then the switching fabric moves the data, and then we repeat. The key challenge he pointed to was power - both in terms of getting energy in (modern CPUs/GPUs take similar current to your car starter motor!) and also getting the heat out. Logic gates take a lot more power than RAM, so he argued that collocating small chunks of RAM right next to your processing core was much better from a power perspective (meaning you could then pack yet more into your chip) as well as obviously being better from a performance perspective. https://www.youtube.com/watch?v=Gh-Tff7DdzU https://www.youtube.com/watch?v=Gh-Tff7DdzU isn't quite the presentation I saw, but it has quite a lot of overlap. Hope that helps!