I don’t think implementation details are relevant for CISC vs RISC. At least not anymore. I think it’s a characteristic of CPU’s instruction set. Not the intern

I don’t think implementation details are relevant for CISC vs RISC. At least not anymore. I think it’s a characteristic of CPU’s instruction set. Not the internal undocumented instructions, but the instructions publically available to programmers. Also, ARM says their CPU designs are based on RISC principles: https://developer.arm.com/products/architecture/cpu-architecture https://developer.arm.com/products/architecture/cpu-architec...