4 ms·

> The hardware prefetch is not really efficient when N>7, because each list element is spread over several cache lines, plus the prefetching is not able to cros

> The hardware prefetch is not really efficient when N>7, because each list element is spread over several cache lines, plus the prefetching is not able to cross page boundaries. Could you explain the first part of the sentence (about the list elements spreading over several cache lines)? It's true that the elements do not fit into a cache line for N>7. But is that important for the prefetcher? Shouldn't the regular access pattern to the "en.n" be detected by the streamer prefetcher (without shuffling, of course)?

mini_marcel 9y ago
Hi, thanks for your question. You're right, this is exactly why a few paragraphs later I doubt about that statement, saying that the prefetcher is certainly not reading the entire array and may act exactly like N=7. I think that this is more about the fact that the prefetcher can't cross page boundaries. That's still right for N<7, though. I still have to dig on this part :) Thanks again!
- tralarpa 9y ago
  This page http://hexus.net/tech/reviews/cpu/37989-intel-core-i7-3770k-22nm-ivy-bridge/?page=2 http://hexus.net/tech/reviews/cpu/37989-intel-core-i7-3770k-... claims that i7 CPUs have a "next-page prefetcher". I don't know how different i5 and i7 are. Do you think your i5 CPU doesn't have it?
  - mini_marcel 9y ago
    Sorry for the delay, I took some time to perform additional researches. What I found is that my i5 has the code name "Products formerly Haswell". I don't exactly know if it has the "next-page prefetcher", but I would say yes. Looking at the document that a reader on Medium linked to me https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf https://software.intel.com/sites/default/files/managed/9e/bc... it looks like the NPP has been introduced into the IVY Bridge family (paragraph 2.4.7), and the paragraph 2.3 says: "The Haswell microarchitecture builds on the successes of the Sandy Bridge and Ivy Bridge microarchitectures.". That said, how the NPP is working is not really clear. I'd say it's maybe more about prefetching the next page to avoid a TLB misses. In this document I didn't found any statement about crossing a page boundary during data prefetches.

mini_marcel 9y ago

Hi, thanks for your question. You're right, this is exactly why a few paragraphs later I doubt about that statement, saying that the prefetcher is certainly not reading the entire array and may act exactly like N=7. I think that this is more about the fact that the prefetcher can't cross page boundaries. That's still right for N<7, though. I still have to dig on this part :) Thanks again!

tralarpa 9y ago
This page http://hexus.net/tech/reviews/cpu/37989-intel-core-i7-3770k-22nm-ivy-bridge/?page=2 http://hexus.net/tech/reviews/cpu/37989-intel-core-i7-3770k-... claims that i7 CPUs have a "next-page prefetcher". I don't know how different i5 and i7 are. Do you think your i5 CPU doesn't have it?
- mini_marcel 9y ago
  Sorry for the delay, I took some time to perform additional researches. What I found is that my i5 has the code name "Products formerly Haswell". I don't exactly know if it has the "next-page prefetcher", but I would say yes. Looking at the document that a reader on Medium linked to me https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf https://software.intel.com/sites/default/files/managed/9e/bc... it looks like the NPP has been introduced into the IVY Bridge family (paragraph 2.4.7), and the paragraph 2.3 says: "The Haswell microarchitecture builds on the successes of the Sandy Bridge and Ivy Bridge microarchitectures.". That said, how the NPP is working is not really clear. I'd say it's maybe more about prefetching the next page to avoid a TLB misses. In this document I didn't found any statement about crossing a page boundary during data prefetches.