5 ms·
The '=' sign is used because after that statement the variable will indeed have equality with the r-value. Coincidentally in async languages like Verilog there
by slededit 9y ago
The '=' sign is used because after that statement the variable will indeed have equality with the r-value.
Coincidentally in async languages like Verilog there is a another assignment operator '<=' which means that the variable won't take the new value until the next clock cycle (or more explicitly the next evaluation of the process block). '=' exists also and has the same meaning as with traditional languages.
- paulddraper 9y agoBy that logic, a <= 1 Should set a to the minimum of a and 1. I.e. after that statement the variable will indeed be less than or equal to the RHS.
- slededit 9y agoLanguages borrowing the syntax don't need to follow its logical consistency. I just thought it was an interesting anecdote.
- deleted 9y ago[deleted]
- lionel- 9y agoWhat about `a = a + 1`?
- slededit 9y agoThe r-value is ephemeral it doesn't exist once the statement ends.