It could work in a backwards compatible manner like a lot of things. That could technically even be handled transparently by hardwiring caches for usage in Rin

It could work in a backwards compatible manner like a lot of things. That could technically even be handled transparently by hardwiring caches for usage in Ring 3 or Ring 0 and then introducing additional opcode for explicitly allowing certain addresses to be put into Ring 3 cache when it goes into Ring 0 cache. PCID already does per-process caching, somewhat, though it's a bit neutered atm. The good thing is that it only needs to be backwards compatible in the sense that an OS that has no idea about this should at worst have a performance penalty. The hard point will be the additional hardware. L2 cache is expensive, L1 even moreso.