AFAIK silicon has a crystalline structure which causes wafers to break on straight lines and at right angles. This might make things difficult for non-rectangul

AFAIK silicon has a crystalline structure which causes wafers to break on straight lines and at right angles. This might make things difficult for non-rectangular parts. There's also a ton of practical issues regarding the process. Photolithography equipment, cutting the wafers, the machines handling and packaging the chips. All would have to be redesigned and I'm sure that would cost more than the saved silicon during the lifetime of the whole plant. The current chip sizes are already getting pretty close to hard limits (speed of light, etc). 900 mm^2 is 30 mm across, which is about half of the distance light travels in a clock cycle (async/clockless circuitry could help here). Larger chips are also less efficient. A while ago I was discussing power efficiency with a HW designer working on memory controllers and he was using a fancy unit called "nanojoules per bit-millimeter", ie. how much energy it takes to flip a bit that is physically located a certain distance away. The efficiency gets much worse as distance increases. Increasing wafer size also improves the yield, which is why Intel has an advantage with 12" wafers (others have 10"). Instead of creating larger chips, the current trend seems to be about packaging more chips in a single package and connecting them more efficiently. In particular, it's about bringing memory closer to the CPU to get those bit-millimeters down.