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Chips are fabb'd on a large wafer, which is then split up (see here: https://s3.amazonaws.com/ksr/assets/003/150/280/9b6a64c4d8ed23068b87cd56737810ca_large.jpg?
by KaiserPro 9y ago
Chips are fabb'd on a large wafer, which is then split up (see here: https://s3.amazonaws.com/ksr/assets/003/150/280/9b6a64c4d8ed23068b87cd56737810ca_large.jpg?1421462097 https://s3.amazonaws.com/ksr/assets/003/150/280/9b6a64c4d8ed... )
Now, the process isnt perfect, and you hear a lot about "yield" Which is basically how many chips on a wafer are not working to spec. Now, as you make a chip bigger, you increase the chance of a mistake. This reduces the "yield" and drives up the cost. (I'm not sure if its actually possible to make a full sized wafer without a mistake, I'll defer that to someone who knows)
In some cases those broken chips arn't all that bad, so they are shipped with the broken bits deactivated (This could be lies, but I think some AMD procs were done like this )
yes, there are other factors like propagation time, but thats solved by not having chip wide cache coherency.
- colejohnson66 9y ago> In some cases those broken chips arn't all that bad, so they are shipped with the broken bits deactivated (This could be lies, but I think some AMD procs were done like this ) That’s called “binning”
- sp332 9y agoYou don't increase the chance of a mistake, you increase the cost of a mistake because each little defect means you're throwing out a whole chip. The larger each chip is, the more expensive each little defect is. Sony had a hard time when they were ramping up Cell processor production, so they designed the chips with 8 SPEs but only shipped them with 7 activated. That way if a defect happened to be in one of the SPEs, they could just turn it off and still ship the chip.