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The "aperture size" in semiconductor manufacturing is a the practical limiting factor in chip size, and some chips (GPUs in particular) are already at the limit
by exDM69 9y ago
The "aperture size" in semiconductor manufacturing is a the practical limiting factor in chip size, and some chips (GPUs in particular) are already at the limit. It's basically the maximum size of the photolithography process (my understanding of semiconductor manufacturing is a bit weak).
Aperture size can be increased to some degree for future manufacturing nodes, but there's a limit to how practical it is.
Other factors also come into play. The distance light travels in a clock cycle has already been mentioned as a hard limit.
Cost is another matter: chips are rectangular but wafers are round. The larger the chips, the more there is wasted area the lower the yield per wafer. Intel has an advantage here, because they use 12" wafers when the rest of the industry uses 10" (this was a few years ago, things may have changed). Historically speaking, these wafers are huge compared to the 4" and 6" wafers of the past. Making the silicon ingots to cut the wafers from is another form of art, modern ingots are HUGE blobs of pure silicon.
I recommend paying a visit to Intel museum if you're around Silicon Valley. It's not a huge museum but has lots of interesting information, nice guides and a great photo-op to take a selfie with a big honkin' chunk of silicon (they've got full ingots and wafers on display).
- dzdt 9y agoAny reason why chips couldn't be hexagonal or triangular? Either one would still tile a wafer, and go closer to a round edge.
- slededit 9y agoYou can't start a saw in the middle of a wafer. You need to cut from end to end.
- yjftsjthsd-h 9y agoTriangles would work for that.
- slededit 9y agoThe area around the acute angles would be almost useless due to lack of routing space.
- jonhendry18 9y agoWhat about laser or a waterjet cutter?
- exDM69 9y agoAFAIK silicon has a crystalline structure which causes wafers to break on straight lines and at right angles. This might make things difficult for non-rectangular parts. There's also a ton of practical issues regarding the process. Photolithography equipment, cutting the wafers, the machines handling and packaging the chips. All would have to be redesigned and I'm sure that would cost more than the saved silicon during the lifetime of the whole plant. The current chip sizes are already getting pretty close to hard limits (speed of light, etc). 900 mm^2 is 30 mm across, which is about half of the distance light travels in a clock cycle (async/clockless circuitry could help here). Larger chips are also less efficient. A while ago I was discussing power efficiency with a HW designer working on memory controllers and he was using a fancy unit called "nanojoules per bit-millimeter", ie. how much energy it takes to flip a bit that is physically located a certain distance away. The efficiency gets much worse as distance increases. Increasing wafer size also improves the yield, which is why Intel has an advantage with 12" wafers (others have 10"). Instead of creating larger chips, the current trend seems to be about packaging more chips in a single package and connecting them more efficiently. In particular, it's about bringing memory closer to the CPU to get those bit-millimeters down.
- deepnotderp 9y agoFwiw, electrical signals in global interconnects move at about half the speed of light. Near speed of light signaling techniques like transmission lines can be used, but aren't due to a variety of reasons.
- deepnotderp 9y agoSilicon wafers are much easier to manufacture in a circle shape.