Yes Agners doc is wrong or perhaps misleading here. He mentions that for loads and stores he tested a loop of load and store to the same location (essentially e

Yes Agners doc is wrong or perhaps misleading here. He mentions that for loads and stores he tested a loop of load and store to the same location (essentially essentially testing store forwarding latency) to get the latency of that pair and then "arbitrarily divided" the measured latency between the load and the store. He did that because to measure the latency of a single instruction the "domain" (eg GP register, SIMD register memory, etc)) of the input(s) as to be the same as the output. Stores have memory output but register/address input so it isn't really possible to measure the latency of a store in isolation. That's why Agners paired up loads and stores to get a latency figure and did the arbitrary split. All that out of the way, it is possible to measure the latency of a load, at least for the load-to-address path like you mention with a pointer chasing load. That latency is 4 cycles minimum on all modern Intel. Add extra 1 cycle each for complex addressing modes or vector loads. So yeah, a load latency of 2 is nonsense for modern Intel. Even talking about the latency is also nonsense since all the loads are independent so it's the throughput, not the latency that matters. IIRC some chips have had 2 cycle L1 accesses: some P4 designs and one of the semi-recent POWER chips.