You don't understand TLB. It is distinctly not a hardware problem. A TLB is a content addressable memory and the mappings and flushing are done by.. software.

You don't understand TLB. It is distinctly not a hardware problem. A TLB is a content addressable memory and the mappings and flushing are done by.. software. You flush it every time you context switch, and pretty much fully all the time with KPTI now that PCID's 4096 ASIDs can't safely save anything other than the kernel and runnable process. My point about madvise protects against PHKs post claiming memory pool objects will always be paging in and out, which is false and again a memory pool is desirable for certain uses as it guarantees maximum latency and avoids very heavy locking in the VFS for high concurrency.