7 ms·
How are they going to fix it without some performance penalty. If the memory is in cache isn't there going to be a timing difference? or an extra check will hav
by samfisher83 9y ago
How are they going to fix it without some performance penalty. If the memory is in cache isn't there going to be a timing difference? or an extra check will have to be made which is going to have to slow down the lookup?
- swsieber 9y agoFrom what I underst and this fixes variants two and three which are cross ring and cross process data extraction. I believe their hardware mitigation is to separate the caches between those (or something to that effect). So there will still be a minor penalty hit for running multiple identical process compared to before. That's my interpretation though, I don't know enough to say that's the correct interpretation.
- Someone1234 9y agoDoes the hardware on x86 even know which cache is owned by which process? It knows which is elevated (kernel Vs. User Vs. Hypervisor, etc) but process isolation on x86 is largely a kernel API construct rather than a hardware one. Unless I'm mistaken.
- rzzzt 9y agoThe answer is yes, if the processor supports PCID: https://news.ycombinator.com/item?id=16094349 https://news.ycombinator.com/item?id=16094349 Simplistically, it allows TLB-cached page table contents to be tagged with a context identifier, and limits the lookups in the TLB to only match within the currently allowed context. TLB cached entires with a different PCID will be ignored.
- hansendc 9y agoI think you are confusing the TLB and processor data caches. PCIDs exist for virtual addresses and are implemented in the TLB, not the processor caches. The processor caches are physically indexed, not virtually indexed. So, does the processor cache have a mechanism to tell which "process" to which a given line belongs? Nope. Two processes (or a process and the kernel) that share memory can be in two PCIDs, but share the processor caches.
- rzzzt 9y agoYou are correct. My assumption was that the original question is not focused on the data cache itself, and so the DTLB does qualify for "knowing" what belongs to which context.
- deleted 9y ago[deleted]
- bitL 9y ago> to fix it without some performance penalty. 10nm + higher frequency?
- PeterisP 9y agoAn additional check can be made in the same time in parallel if there's extra hardware (specific gates) assigned to do that.