I think most HDLs are approaching the diminishing returns of abstraction already. Most of the electrical characteristics are already captured in routing, setup

I think most HDLs are approaching the diminishing returns of abstraction already. Most of the electrical characteristics are already captured in routing, setup and hold times so while you may not directly interact with them anything more than the most trivial design will be constrained by them. By "under the hood" I was referring to the constraints you have on what you design. In the software space we are mostly constrained by memory(huge), network speed(blazing fast), CPU time(tasks running long normally don't break things). In FPGA/ASIC land those constraints are much, much smaller(kB vs gB) and there are many more(thermals, power, hard cycle requirements, etc).