Sometimes if-else-chaining is what you need. But if you are doing one of n-select, a switch is what you should use. If you are using Verilog 2001 or later, you

Sometimes if-else-chaining is what you need. But if you are doing one of n-select, a switch is what you should use. If you are using Verilog 2001 or later, you can use always @* to implicitly declare all variables a combinational process depends on. It used to be a huge source of latches. I would also highly advice against mixing blocking (i.e a = x) and non-blocking (i.e. a <= x) assignments in one process. I usually write a single clocked process with all registers and then only have a few extra combinational processes for the logic. I also recommend separating data path logic (the processing you do) with the control path (the FSM that keep track of what is happening inside your machine). Never assume values or states is really good. I usually assign default states at the top of processes. Then for other state you only have to define that. It is really helpful in FSMs. Not claiming to having a great coding style, but if you want some examples on RTL code and testbenches here are my cores for AES, SHA256 and many others: https://github.com/secworks https://github.com/secworks