It's not just the cost, at least not just the cost of the RAM. GPU ram is designed to be wider than desktop memory, meaning that you need more pins on the die f

It's not just the cost, at least not just the cost of the RAM. GPU ram is designed to be wider than desktop memory, meaning that you need more pins on the die for the same amount of memory. The IO in top end accelerators uses all the real estate available for pins, and the dies are already at the reticle limit, so to add memory you have to either: 1) Use desktop memory that allows more BW/pin but is also much slower per pin 2) Develop completely new memory just for your application 3) Put some kind of buffering between the chip and the ram, greatly increasing latency. None of these is currently that appealing for the manufacturers. HMC was originally going to do 3 by doing 2, but HMC appears stillborn, as all the momentum went to HBM instead, and HBM cannot increase the memory count per pin nearly as much as HMC could.