3 ms·

Tl;dr, as far as I can tell: Context switch performance can be improved by abolishing registers. Also, here's some indications that this won't necessarily compl

Tl;dr, as far as I can tell: Context switch performance can be improved by abolishing registers. Also, here's some indications that this won't necessarily completely annihilate processor performance.

woadwarrior01 9y ago
Which sounds a bit like implementing the LLVM IR as an ISA. You don't have registers, but instead you get an infinite number of temporary values.
- bob_rad 9y ago
  You mean SSA right? Just about every compiler has a point at which all registers are a finite list of values (usually up to max int).
jcranmer 9y ago
It certainly took a long time for the paper to get to any sort of point. The beginning of the paper is a well-trod (for anyone who's looked at computer architecture) commentary that "VLIW doesn't work," "delay slots don't work," and "the MIPS let-the-compiler-figure-out-register-interlocking doesn't work." So the brunt of the paper is the idea that replace registers with memory. Except: * The overarching goal is making context switch overheads go away. Except isn't the expensive part of the context switch flushing the TLB and all the caches? * A register file on an x86/POWER-kind of processor has something like a dozen ports and 1 clock cycle latency. The L1 cache has 4 clock cycle latency (on a hit) and about two ports. Ports are expensive, even more so on large memory banks (such as a cache). * At three memory operations (two reads and one write) per instruction, and hopefully 1-2 instructions per cycle, you're really hammering on the cache coherency traffic. The paper does suggest making the cache incoherent. * Given the expense of doing virtual memory lookup, and the probably need for cache incoherence, it may make sense to make the main stack effectively physically tagged within a function and make the compiler emit offsets within the cache. At this point, you have a block of memory that's indexed independently of main memory, and doesn't communicate with main memory most of the time, and is meant to be accessed as frequently as a register file. Well, it basically is a register file at that point. The only thing you're adding is the ability to dump and read the register file to main memory at specified points.

Tl;dr, as far as I can tell: Context switch performance can be improved by abolishing registers. Also, here's some indications that this won't necessarily completely annihilate processor performance.

woadwarrior01 9y ago

Which sounds a bit like implementing the LLVM IR as an ISA. You don't have registers, but instead you get an infinite number of temporary values.

bob_rad 9y ago
You mean SSA right? Just about every compiler has a point at which all registers are a finite list of values (usually up to max int).

jcranmer 9y ago

It certainly took a long time for the paper to get to any sort of point. The beginning of the paper is a well-trod (for anyone who's looked at computer architecture) commentary that "VLIW doesn't work," "delay slots don't work," and "the MIPS let-the-compiler-figure-out-register-interlocking doesn't work." So the brunt of the paper is the idea that replace registers with memory. Except: * The overarching goal is making context switch overheads go away. Except isn't the expensive part of the context switch flushing the TLB and all the caches? * A register file on an x86/POWER-kind of processor has something like a dozen ports and 1 clock cycle latency. The L1 cache has 4 clock cycle latency (on a hit) and about two ports. Ports are expensive, even more so on large memory banks (such as a cache). * At three memory operations (two reads and one write) per instruction, and hopefully 1-2 instructions per cycle, you're really hammering on the cache coherency traffic. The paper does suggest making the cache incoherent. * Given the expense of doing virtual memory lookup, and the probably need for cache incoherence, it may make sense to make the main stack effectively physically tagged within a function and make the compiler emit offsets within the cache. At this point, you have a block of memory that's indexed independently of main memory, and doesn't communicate with main memory most of the time, and is meant to be accessed as frequently as a register file. Well, it basically is a register file at that point. The only thing you're adding is the ability to dump and read the register file to main memory at specified points.