The bottleneck for DDR memory isn't really the memory controller but rather the memory bus itself. Moving the controller won't change that. Its very rare to g

The bottleneck for DDR memory isn't really the memory controller but rather the memory bus itself. Moving the controller won't change that. Its very rare to get anywhere close to 100% bus utilization. HMC's real advance is switching to independent serial links which we know how to scale better than parallel busses. Its this improved bandwidth that allows you to pack in more parallelism. We could have more banks in traditional DDR memory but there isn't much point because the data bus couldn't feed it.