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FWIW DDR3 includes 8 banks each of which can execute independently of the others. So there is still parallelism there. DDR4 doubles this to 16.
by slededit 9y ago
FWIW DDR3 includes 8 banks each of which can execute independently of the others. So there is still parallelism there. DDR4 doubles this to 16.
- dragontamer 9y ago> FWIW DDR3 includes 8 banks each of which can execute independently of the others. So there is still parallelism there. DDR4 doubles this to 16. Indeed. So there's some parallelism that can be captured, but they're managed by the CPU instead of the Memory. Because HMC abstracts away the protocol into a packet-based innately out-of-order protocol, and because the "memory controller logic" has been moved to an area physically as-close-as-possible to the RAM itself, it can achieve much higher degrees of parallelism. Case in point: a single stack of HMC has 128 banks of parallelism across 4-vaults (I would argue that a "vault" is roughly equivalent to a DDR4 channel): https://www.micron.com/parts/hybrid-memory-cube/hmc-sr/mt43a4g40200nfa-s15?pc={8AD36F73-07F4-4ECD-A168-B5E899F1E650} https://www.micron.com/parts/hybrid-memory-cube/hmc-sr/mt43a...
- slededit 9y agoThe bottleneck for DDR memory isn't really the memory controller but rather the memory bus itself. Moving the controller won't change that. Its very rare to get anywhere close to 100% bus utilization. HMC's real advance is switching to independent serial links which we know how to scale better than parallel busses. Its this improved bandwidth that allows you to pack in more parallelism. We could have more banks in traditional DDR memory but there isn't much point because the data bus couldn't feed it.