> An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards. Each bit being complete

> An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards. Each bit being completely independent seems to make it trivial to parallelise. I know they describe it as "serial" but I don't see anything inherently serial about it. High order numbers being impractical anyway means in practical use people would probably settle on predefined word lengths rather than actual "bit streams". You can multiply your 256bit word (8bit probabilistic integer) in the time it takes to propagate through a single AND gate - the shortest possible, giving you the fastest clock - or if sharing the clock with other far more time consuming blocks in traditional CPUs it allows you to do a great many probabilistic multiplications in a single clock with the same silicon in the same block. Admittedly what i'm suggesting uses 256 gates not a dozen, but the performance will be significantly better in terms of how much clock it takes up. I think the real problem with this method is the cost of serialising into the probabilistic bit stream. That needs to be avoided as much as possible to make this useful.