4 ms·

“An AND gate is a digital circuit with two inputs and one output that gives a 1 only if both inputs are 1. It consists of just a few transistors and requires ve

by dfee 9y ago

“An AND gate is a digital circuit with two inputs and one output that gives a 1 only if both inputs are 1. It consists of just a few transistors and requires very little energy to operate. Being able to do multiplications with it—rather than, say, programming a microprocessor that contains thousands if not millions of transistors—results in enormous energy savings.” To be fair, you don’t need thousands or millions of transistors for a functional ALU, such as the ones we built in college. I’d imagine the reason it’s more practical to use something with 1M transistors rather than something with 10 or 100 is the ease of integration, (amazingly) simplified manufacturing, and supply chains already existing. I.e. why not throw a 1M transistors in when it’s actually cheaper? So then, I’m sure there is value in what’s proposed, but for a layperson, what is the real, practical advantage of this?

tonmoy 9y ago
To save power I guess
josephg 9y ago
The practical advantage the article describes is in power consumption. Transistors are small and cheap, but in aggregate they're power hungry. This makes them work less well on the tiny voltages you can extract inside someone's eye, for example. Mind you, modern low power chips use absolutely minuscule amounts of power. I suspect this technique will need a lot of refinement before its actually competitive.
- st26 9y ago
  I suspect this technique will need a lot of refinement before its actually competitive. The main trouble with this technique, I suspect, is it doesn't get at the root of where power is really spent. Yes, anything costs power, but is that where all the juice is really going? A famous stat from the P4 days was, 40% of chip power was spent just driving the clocks. I'm sure it's better today, but how much? What about all the leakage in the SRAMs?
  - kakarot 9y ago
    I don't have any stats on modern power consumption, but to be fair the P4 was an experiment in higher clock speeds that didn't pan out. Future processors focused on increased parallelization and returned to less power-hungry clock speeds.
userbinator 9y ago
To be fair, you don’t need thousands or millions of transistors for a functional ALU, such as the ones we built in college. Indeed, and some of the variants of early mainframes were bit-serial in order to reduce cost, with a corresponding (significant) decrease in performance too. An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards, but there's a reason bit-serial processors have basically become extinct: they're horribly slow. Any power savings is negated by the multiple-times-longer every operation takes, so the total energy does not decrease. In fact, since now frequency has to increase, and power consumption increases superlinearly with frequency, it's a net loss. One memorable microcontroller with a bit-serial ALU is the CDP1802 --- and it takes 16 clock cycles for a single 8-bit add instruction.
- skybrian 9y ago
  I wonder how the technique described in the article would compare to working with DSP chips? Say you have two continuous streams of numbers and want to add them. So, the processor is always on, it's constantly receiving numbers and adding them, and there is no "race to idle"; it's more a matter of power consumption and response time.
- tomxor 9y ago
  > An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards. Each bit being completely independent seems to make it trivial to parallelise. I know they describe it as "serial" but I don't see anything inherently serial about it. High order numbers being impractical anyway means in practical use people would probably settle on predefined word lengths rather than actual "bit streams". You can multiply your 256bit word (8bit probabilistic integer) in the time it takes to propagate through a single AND gate - the shortest possible, giving you the fastest clock - or if sharing the clock with other far more time consuming blocks in traditional CPUs it allows you to do a great many probabilistic multiplications in a single clock with the same silicon in the same block. Admittedly what i'm suggesting uses 256 gates not a dozen, but the performance will be significantly better in terms of how much clock it takes up. I think the real problem with this method is the cost of serialising into the probabilistic bit stream. That needs to be avoided as much as possible to make this useful.

by dfee 9y ago

tonmoy 9y ago

To save power I guess

josephg 9y ago

The practical advantage the article describes is in power consumption. Transistors are small and cheap, but in aggregate they're power hungry. This makes them work less well on the tiny voltages you can extract inside someone's eye, for example. Mind you, modern low power chips use absolutely minuscule amounts of power. I suspect this technique will need a lot of refinement before its actually competitive.

st26 9y ago
I suspect this technique will need a lot of refinement before its actually competitive. The main trouble with this technique, I suspect, is it doesn't get at the root of where power is really spent. Yes, anything costs power, but is that where all the juice is really going? A famous stat from the P4 days was, 40% of chip power was spent just driving the clocks. I'm sure it's better today, but how much? What about all the leakage in the SRAMs?
- kakarot 9y ago
  I don't have any stats on modern power consumption, but to be fair the P4 was an experiment in higher clock speeds that didn't pan out. Future processors focused on increased parallelization and returned to less power-hungry clock speeds.

userbinator 9y ago

To be fair, you don’t need thousands or millions of transistors for a functional ALU, such as the ones we built in college. Indeed, and some of the variants of early mainframes were bit-serial in order to reduce cost, with a corresponding (significant) decrease in performance too. An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards, but there's a reason bit-serial processors have basically become extinct: they're horribly slow. Any power savings is negated by the multiple-times-longer every operation takes, so the total energy does not decrease. In fact, since now frequency has to increase, and power consumption increases superlinearly with frequency, it's a net loss. One memorable microcontroller with a bit-serial ALU is the CDP1802 --- and it takes 16 clock cycles for a single 8-bit add instruction.

skybrian 9y ago
I wonder how the technique described in the article would compare to working with DSP chips? Say you have two continuous streams of numbers and want to add them. So, the processor is always on, it's constantly receiving numbers and adding them, and there is no "race to idle"; it's more a matter of power consumption and response time.
tomxor 9y ago
> An ALU can be less than a dozen transistors or so if it's completely serial --- which seems to be what this article is going towards. Each bit being completely independent seems to make it trivial to parallelise. I know they describe it as "serial" but I don't see anything inherently serial about it. High order numbers being impractical anyway means in practical use people would probably settle on predefined word lengths rather than actual "bit streams". You can multiply your 256bit word (8bit probabilistic integer) in the time it takes to propagate through a single AND gate - the shortest possible, giving you the fastest clock - or if sharing the clock with other far more time consuming blocks in traditional CPUs it allows you to do a great many probabilistic multiplications in a single clock with the same silicon in the same block. Admittedly what i'm suggesting uses 256 gates not a dozen, but the performance will be significantly better in terms of how much clock it takes up. I think the real problem with this method is the cost of serialising into the probabilistic bit stream. That needs to be avoided as much as possible to make this useful.