keep in mind that raw speed (in terms of say, ram access or PCI-E access (which is already faster than this implementation)) is rarely the obsticle these days,

keep in mind that raw speed (in terms of say, ram access or PCI-E access (which is already faster than this implementation)) is rarely the obsticle these days, the issue is fetch/rtt latency, especially with trying to integrate FPGA acceleration into a codebase for offloading some operations, the penalty for for which can often be tens of thousands of cycles, or more.