3 ms·

guys, I'll be honest: I found it really odd that the article didn't talk about the speed of light, and die size constraints. (c / 4 ghz = 7.49 cm only, if you

guys, I'll be honest: I found it really odd that the article didn't talk about the speed of light, and die size constraints. (c / 4 ghz = 7.49 cm only, if you double that frequency you have half that size to put components it between any two clock ticks.) But there are limits to my hubris - this is on intel.com, so I'm going to go with "I'm the one missing something". Is the speed of light and number of transistors you can put in that path (due to die size) just not a practical constraint? Neither is mentioned.

pjc50 9y ago
The key factors in integrated circuit delay are more to do with capacitance; in order to change a gate's transistor from off to on, the driving gate has to charge the capacitance of the driving wire and the driven gate. Making features closer together increases their mutual capacitance. (source: worked on this for a chip design software company. The delay approximation was based entirely around R/L/C modelling and had no terms for the speed of light per se. If I remember rightly it was calculated in integer pico-meters; I definitely remember it emitting an error message if you had more than 2cm of wire in any one net!)
- v_lisivka 9y ago
  I.e. the problem is the state of processor, which need to be erased. So we can make stack of stateless processors, which will readily accept fresh data, because they will need to fill capacitors only, not discharge, and then discharged after use. Kind of multicore design, but with each core used for only 1/n of time at e.g. 1Thz frequency. Unlike parallel system, sequential calculation will work faster in such setup.
  - rcxdude 9y ago
    discharging and charging capacitance is generally pretty symmetric. I don't think what you're suggesting would provide much benefit.
    - v_lisivka 9y ago
      But heating and cooling is not symmetrical. We can heat a processor much faster than cool it. So, if we need to cool a processor 10x faster than we can, just use 10x more processors, and switch them in order, to allow them cool after use in overclocked mode. Using this simple technique, frequency can be raised by few GHz, which is important for serial computations.
  - pjc50 9y ago
    .. what? No, the capacitance issue is inherent in any kind of electrical signal sent over wires.
AnimalMuppet 9y ago
To amplify what pcj50 said: The speed of light is a very real constraint. It's just not the constraint that people are hitting, because there are other constraints you hit first (capacitance, heating, etc). I recall reading clear back in the 1970s that IBM mainframes were trying to do a dual processor setup. This wasn't multiple cores on one die, this was separate physical boxes. And they were having trouble because they wanted them to operate in sync (in the sense of presenting one image to the OS and applications), but they were more than a foot apart, and they were operating at sub-nanosecond frequencies. For them, the speed of light was definitely a constraint. Even if they got around all the electrical stuff, the speed of light still put a limit on how "in sync" those two CPUs could be.

pjc50 9y ago

The key factors in integrated circuit delay are more to do with capacitance; in order to change a gate's transistor from off to on, the driving gate has to charge the capacitance of the driving wire and the driven gate. Making features closer together increases their mutual capacitance. (source: worked on this for a chip design software company. The delay approximation was based entirely around R/L/C modelling and had no terms for the speed of light per se. If I remember rightly it was calculated in integer pico-meters; I definitely remember it emitting an error message if you had more than 2cm of wire in any one net!)

v_lisivka 9y ago
I.e. the problem is the state of processor, which need to be erased. So we can make stack of stateless processors, which will readily accept fresh data, because they will need to fill capacitors only, not discharge, and then discharged after use. Kind of multicore design, but with each core used for only 1/n of time at e.g. 1Thz frequency. Unlike parallel system, sequential calculation will work faster in such setup.
- rcxdude 9y ago
  discharging and charging capacitance is generally pretty symmetric. I don't think what you're suggesting would provide much benefit.
  - v_lisivka 9y ago
    But heating and cooling is not symmetrical. We can heat a processor much faster than cool it. So, if we need to cool a processor 10x faster than we can, just use 10x more processors, and switch them in order, to allow them cool after use in overclocked mode. Using this simple technique, frequency can be raised by few GHz, which is important for serial computations.
- pjc50 9y ago
  .. what? No, the capacitance issue is inherent in any kind of electrical signal sent over wires.

AnimalMuppet 9y ago

To amplify what pcj50 said: The speed of light is a very real constraint. It's just not the constraint that people are hitting, because there are other constraints you hit first (capacitance, heating, etc). I recall reading clear back in the 1970s that IBM mainframes were trying to do a dual processor setup. This wasn't multiple cores on one die, this was separate physical boxes. And they were having trouble because they wanted them to operate in sync (in the sense of presenting one image to the OS and applications), but they were more than a foot apart, and they were operating at sub-nanosecond frequencies. For them, the speed of light was definitely a constraint. Even if they got around all the electrical stuff, the speed of light still put a limit on how "in sync" those two CPUs could be.