I think there is another fix: avoid all normal loads and stores to cache lines that contain atomic data structures. When allocating the data structure, make su

I think there is another fix: avoid all normal loads and stores to cache lines that contain atomic data structures. When allocating the data structure, make sure to grab a whole cache line or more. Flush and invalidate that, even if you have to do the entire cache. Now simply use the LL/SC operations (apparently named LDREX/STREX on ARM) exclusively. The bug will protect you from itself, preventing the data structure from ever being cached. The only danger left is that some processors will predict memory access, leading to a speculative load of the cache line. I don't know if this CPU has such a feature. If so, a larger allocation might be needed.