3 ms·
The M4, to my knowledge, has no microcode like x86 processors. For solution (b), while it can't be guaranteed by the compiler, it can be guaranteed with extern
by rschaefer2 9y ago
The M4, to my knowledge, has no microcode like x86 processors.
For solution (b), while it can't be guaranteed by the compiler, it can be guaranteed with external tooling that manually ensures that all atomic variables have a gcc section attribute specifying the linker section in the TCM when all sources are available. This also will prevent heap and stack allocated atomics, as I believe the linker will error when specifying a section attribute that the linker cannot respect.
Solution (c), that is actually the solution developed for use with some M0 implementations that don't support LL/SC. It works with gcc as the gcc functions implementations have the __weak attribute, meaning that your implementation takes priority. An example override of fetch_add:
uint32_t __atomic_fetch_add_4(uint32_t* addr, uint32_t value, int memmodel)
{
(void)memmodel;
uint32_t mask = __get_PRIMASK();
__disable_irq();
uint32_t temp = *addr;
*addr = temp + value;
if (mask) {
__enable_irq();
}
return temp;
}