4 ms·
Maybe I'm just blind, but I can't find a link to the paper in the press release. Not that I would understand the hardware-specific parts, but I was just curious
by Asdfbla 9y ago
Maybe I'm just blind, but I can't find a link to the paper in the press release. Not that I would understand the hardware-specific parts, but I was just curious what software implementations they benchmarked against and how their elliptic curve algorithms were implemented.
I guess research chips like those end up serving as inspiration for the CPU designers of Intel/AMD/ARM etc. to evaluate which encryption instruction sets might be good to include in the future? Or are the fast vectorized multiplication operations and such already good enough to implement fast asymmetric crypto and no specialized instructions similar to AES-NI are needed? (Though of course this paper seems to imply that specialized hardware is useful)
- 0xFFC 9y agoAbout first part, I was very interested to read the original paper too but couldn’t find it in the article. This is so unprofessional of MIT Technology News.
- jwfxpr 9y agoThe paper described in this article is not yet presented — it will likely be published in the proceedings of the cyber. But I found two relevant recent publications from the same lead author through Google Scholar: Energy-efficient protocols and hardware architectures for transport layer security — https://dspace.mit.edu/handle/1721.1/111861 https://dspace.mit.edu/handle/1721.1/111861 eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things — http://ieeexplore.ieee.org/abstract/document/8255053/ http://ieeexplore.ieee.org/abstract/document/8255053/ There are probably others. I look forward to seeing this paper when it's published though.