3 ms·

Yes, they can interface with RAM, but usually at a slower speed than a GPU can interface with colocated RAM (I believe, this is a bit out of my expertise)

• dfox 9y ago
  For this kind of workload it makes sense to optimize the DRAM array topology to the problem at hand, which you cannot do on GPU. That obviously means that you cannot use ready made FPGA devboard (which usuallly have quite narrow memory interfaces) but you have to design your own board.
• dragontamer 9y ago
  Your statement is probably true for strictly 3 GPUs: Vega 56, Vega 64, and Titan V. Because those three GPUs use next-generation stacked-die HBM2 memory. Alas: an FPGA or ASIC could ALSO use HBM2 memory (although looking into the RAM types available: Hybrid Memory Cube looks like a better fit for the Cryptocoin Proof-of-Work problems). The main issue is that stacked-memory + interposers require advanced manufacturing techniques and are incredibly expensive right now. But if the future makes this technology cheaper, then I'd expect FPGA + Hybrid Memory Cube to eventually become the ideal platform for Proof-of-Work mining. AMD really did a good job at turning HBM2 into a commodity (well, until HBM2 supplies dried up anyway). ------------- If you're talking about commodity GPUs, well... QDR-IV and RLDRAM3 have way lower latency than GDDR5, DDR4, and GDDR6. So I'd expect RLDRAM3 + FPGAs or ASIcs to beat any GDDR5 or GDDR6 based GPU at memory-hard problems.