3 ms·
Thanks. Is all this learnable from the Intel docs? Or is there a lot of IACA experimentation?
by jnordwick 9y ago
Thanks. Is all this learnable from the Intel docs? Or is there a lot of IACA experimentation?
- BeeOnRope 9y agoMost of this is in Agner's docs (check out microarchitecture.pdf and look for 'fusion') and his spreadsheets (which lists the number of uops in the fused and unfused domains). Once you understand that background see this answer: https://stackoverflow.com/a/31027695/149138 https://stackoverflow.com/a/31027695/149138 which has the most up-to-date info I'm aware of about some important issues that doc doesn't cover (in particular, revealing that there is are actually two types of micro-fusion: the bad kind that unlaminates before renaming, and the good kind that doesn't). IACA is mostly pretty useless for this stuff: or at least I'd never trust it by itself since it fails to correctly model a lot of the various cases (including stuff as basic as L1-hit latency for the various addressing modes). In this case, it actually was IACA that triggered the investigation, so this is a bit of an exception to that - but even here it failed to model it correctly once the details were worked out through testing.
- jnordwick 9y agoThanks so much. It really fills a gap in my knowledge. I do high performance work, so i don't use this directly, but i find it very interesting and feel it improves my mental model of what's going on under the hood. Id also like to dig into compilers a little more than my college courses, and i have an idea for code gen of APL functions used in a particular setting (database stored procs).