4 ms·
I'm not sure about other RISC ISAs, but on RISC-V, register-to-register moves are encoded as "ADDI rd, rs, 0". That is, add 0 (immediate) to rs and store in rd.
by baobrien 9y ago
I'm not sure about other RISC ISAs, but on RISC-V, register-to-register moves are encoded as "ADDI rd, rs, 0". That is, add 0 (immediate) to rs and store in rd. Canonical NOPs are "ADDI x0, x0, 0", where x0 is the hardwired-zero register.
- pcwalton 9y agoThat's a typical RISCism, going back at least to MIPS. Among popular recent ISAs, AArch64 uses a zero register.
- 0xcde4c3db 9y agoMIPS does similar things, except that the NOP is "sll r0, r0, 0", i.e. left-shift the hardwired zero register by zero, and store the result in r0. They presumably chose this over the many other "store in R0" instructions because it encodes to 0x00000000.