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> Their failed 10nm shrink has forced product delays Previously [1], from 2012 (starting around t=49:52): "Lots of problems here [at 11nm]. Intel and IBM have
by ken 9y ago
> Their failed 10nm shrink has forced product delays
Previously [1], from 2012 (starting around t=49:52): "Lots of problems here [at 11nm]. Intel and IBM have publicly discussed solving the problems with 11nm by skipping it", i.e., going straight to 7nm with never-been-used-before EUV lithography.
[1]: https://news.ycombinator.com/item?id=16175949 https://news.ycombinator.com/item?id=16175949
Were people realistically expecting Intel to hit deadlines at 10nm? This sounded more like a research project than a product line.
- epmaybe 9y agoI always got confused with how companies like Intel planned on getting past a 10nm transistor size. How does one get around the issue of electron tunneling at that threshold (or close to that threshold)? Granted, I only understand CPUs and quantum physics at a very abstract level.
- frostburg 9y ago10nm doesn't actually means that the transistors are 10nm-sized
- the8472 9y agoDirect tunneling in the channel becomes a problem < 4nm. the gate insulator can be even thinner since they use high dielectric constant ones which limits the tunneling current. As GP mentioned the main problem with 10nm is the photolithographic process. Currently they're using 193nm ArF lasers. EUV "light" is very difficult to generate and handle. There aren't even lenses for it, only lossy mirrors, so each optics step will lose you a fraction of the input power and heat the mirrors.