4 ms·

Not entirely true. You can generate netlists without going to VHDL/Verilog.

• user20180120 9y ago
  In an ASIC flow, they use C++/SystemC that feeds into High Level Synthesis tools to generate an intermediate auto-machine generated RTL HDL Verilog. This then flows into a digital logic synthesis tool to be converted to a Verilog gate-level netlist. The industry uses a Verilog netlist as a defacto standard that is then put through an implementation flow for place and route, where the aim is to convert the Verilog netlist description of logic gates/D-flops into a physical representation of the final chip in silicon, in the form of a GDSII [GDS2 file] for taping out which in turn is then sent on to a foundry to be manufactured. The manually written HDL RTL either in VHDL or Verilog takes too long to write in terms of human hours by large teams of HDL RTL coding engineers. The aim of using High Level Synthesis is to reduce the time to market for generating a Verilog netlist. When RTL HDL languages first came out in conjunction with digital synthesis tools, many engineers were not believing in the technology, in which they used to do things manually by hand laying out the gates/transistors. Youtube video link from 1977 [watch from at time from 07:52 time mark, manual work done from 9:36 time mark onwards] BBC Horizon: 1977-1978 Now The Chips Are Down [https://youtu.be/HW5Fvk8FNOQ?t=472 https://youtu.be/HW5Fvk8FNOQ?t=472]