3 ms·
Do you have any good source of what these problems are? The reason I am asking is because I too am designing my home-grown HDL at the moment because I grew tire
by moring 9y ago
Do you have any good source of what these problems are? The reason I am asking is because I too am designing my home-grown HDL at the moment because I grew tired of both Verilog and VHDL. Since I never programmed FPGAs professionally -- the whole thing is a pet project only -- I'm likely to repeat those mistakes because I don't even know about them.
Note that I don't expect problems in the basics of language design and building tools, but rather specific mistakes in the context of FPGAs.
- ChickeNES 9y agoI'm curious to know more about your HDL, as I'm also working on an HDL of my own.
- moring 9y agoThe code is at https://github.com/MartinGeisse/mahdl-plugin https://github.com/MartinGeisse/mahdl-plugin Feel free to open an issue on GitHub to start a discussion. (I'm hesitant to post my private email address here -- old habits.)