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Awesome presentation. To me the most magical part is not the manufacturing process, although that is very special, but how a team of engineers designed somethi

Awesome presentation. To me the most magical part is not the manufacturing process, although that is very special, but how a team of engineers designed something which is made up of hundreds of millions of transistors, each in a specific location for a specific reason. How is all of that done? How do they keep track of things? Is there special software?

FPGAhacker 9y ago
There are a number of disciplines involved. Engineers at the foundry will range from those focused keeping the equipment aligned to produce functional structures on/in silicon over time, to engineers that design standard libraries of components to work at a given 'process' (the steps in going from wafer to chip for a given set of parameters/attributes). The structures in silicon (or other semiconductor material) are the transistors mainly. These are created by embedding impurities in geographic locations and patterns in the silicon that change it's conductive properties. Embedding these impurities is called doping. The structures on top of the silicon are conductors and insulators used for interconnecting all the transistors. There will be engineers at the foundry (or a company that works with that foundry) that take a "netlist" from the customer and convert that into files that can be used by mask company to make masks for the layers of conductors and insulators the lay on top of the transistors, and also the patterns for doping the silicon. Engineers at "tool vendors" will build software that takes a high level description of the desired functionality of the chip and turn it into the netlist that foundry engineers can use. The netlist is a decomposition of the high level description (such as x <= a * b) into the components in the "standard library" for that foundry. This library will contain basic components like AND gates and OR gates, but also more complicated things like IO pads and RAMs, and things like multipliers. Then you have design and verification engineers at a given company that wants to build a chip. These tend to stay at the higher level, working in VHDL, Verilog, and SystemVerilog. Which are all pretty archaic by software language standards. And what is considered high level in this arena is about the C language level or below. So not so high from a software point of view. I just spat this out off the top of my head, so apologies if I made mistakes.

FPGAhacker 9y ago

There are a number of disciplines involved. Engineers at the foundry will range from those focused keeping the equipment aligned to produce functional structures on/in silicon over time, to engineers that design standard libraries of components to work at a given 'process' (the steps in going from wafer to chip for a given set of parameters/attributes). The structures in silicon (or other semiconductor material) are the transistors mainly. These are created by embedding impurities in geographic locations and patterns in the silicon that change it's conductive properties. Embedding these impurities is called doping. The structures on top of the silicon are conductors and insulators used for interconnecting all the transistors. There will be engineers at the foundry (or a company that works with that foundry) that take a "netlist" from the customer and convert that into files that can be used by mask company to make masks for the layers of conductors and insulators the lay on top of the transistors, and also the patterns for doping the silicon. Engineers at "tool vendors" will build software that takes a high level description of the desired functionality of the chip and turn it into the netlist that foundry engineers can use. The netlist is a decomposition of the high level description (such as x <= a * b) into the components in the "standard library" for that foundry. This library will contain basic components like AND gates and OR gates, but also more complicated things like IO pads and RAMs, and things like multipliers. Then you have design and verification engineers at a given company that wants to build a chip. These tend to stay at the higher level, working in VHDL, Verilog, and SystemVerilog. Which are all pretty archaic by software language standards. And what is considered high level in this arena is about the C language level or below. So not so high from a software point of view. I just spat this out off the top of my head, so apologies if I made mistakes.