3 ms·
My understanding is that the latest AMD CPUs use a neural net branch predictor which requires that they store the entire address, not just some of the bits, so
by xenadu02 9y ago
My understanding is that the latest AMD CPUs use a neural net branch predictor which requires that they store the entire address, not just some of the bits, so you can’t effectively poison the branch predictor.
Everyone else will switch to the same model.
I suspect that cache changes will need to be tagged with the reorder buffer slot and rolled-back on mis-predict. It also means a hit to the N-way scheme because you must be able to hold multiple instances of the cache line for the same address.
I also worry there are undiscovered side channels lurking in arch-specific registers or status bits.
- phire 9y agoRolling back the cache changes is just asking for trouble. Consider that any cycles you spend undoing cache changes is also a side effect that can potentially be measured. Instead, hold the newly loaded cache lines in a "cache line buffer", the same way how stores are held in a store buffer. For any reads, the CPU will check the cache load buffers before L1 cache. Then once the instruction which triggered the cache read completes, the new cache line will finally be applied to the L1 cache and the old line evicted. In the case of a misprediction, the cache load buffers can be discarded instantly.