5 ms·
> I believe that's not even using the streaming compilation mentioned in the article That's correct. Streaming compilation would finish earlier, but might actu
by callahad 9y ago
> I believe that's not even using the streaming compilation mentioned in the article
That's correct. Streaming compilation would finish earlier, but might actually benchmark more slowly because you'd be adding in the time that the compiler is idle and waiting for the network to catch up.
Preloading the .wasm file in the test lets us measure just the speed of the compiler, independent of the network.
- derefr 9y agoAn interesting benchmark would be the total energy usage of the CPU while loading a page in each browser. The compiler managing to idle waiting for network packets should theoretically allow some of the CPU cores to enter sleep states. (Not all, since others are still busy rendering the page, and at least one is busy doing whatever non-DMA kernel bits are involved with receiving the network packets.)
- etep 9y agoIt should be the case that if the same amount of work is done, then the energy used will be the same. If it takes less work to compile the web assembly, then less energy (holding all other parameters the same). If you have to idle a CPU, then you probably use more energy (holding all other parameters the same) i.e. because you will spend more time and accomplish the same amount of real work (but waste energy on the idled core, albeit waste very little, accomplishing extra, but non-productive, work). Cannot let some other CPU parameter changes as a result of cores being idled (e.g. frequency gets boosted on non-idle cores as a result of dynamic frequency scaling with idle cores) to run this experiment. Thinking about CPU energy use is interesting :)
- yjftsjthsd-h 9y agoI don't think that's true; isn't the relationship between clock speed and power non-linear?
- ethbro 9y agoThat's for max frequency on a given process node. Power scales with voltage squared. But that doesn't say anything about wasted power. And dynamic scaling screws that up in modern chips. I believe I could summarize things by saying the only way you can really save energy* doing the same work+ is by using a different semiconductor process (either power/leakage-reduction-focused or smaller). * For serious values of "energy" + Where the same work is not always true for a given task, if one optimizes an algorithm
- naikrovek 9y agoCan you explain the voltage squared thing? To me, power = voltage * current.
- etep 9y agoFor chips, power scales with voltage squared. Is also true that P=IV (since both are true, these observations cannot be in contradiction). Apparently, for chips, the current must be proportional to voltage also. Glossing over some details, turning on (off) a transistor is the same as charging (discharging) a capacitor. The energy stored on a capacitor is 1/2 C V^2. If you turn on and off the transistor periodically (say with frequency f) you use 1/2 C V^2 energy f times per second (energy per unit time is power). Normally the capacitance is ignored when discussing how power changes because for a given design the capacitance is a fixed quantity.
- Filligree 9y agoRunning a processor at higher frequency also requires increasing voltage, which increases effective capacitance by that same formula. That's not the primary cause of the power = frequency^2 rule, but actually adds a factor on top of that.
- mmwelt 9y agoEven for purely resistive loads, power is proportional to the square of the voltage: P = V * I But, I = V / R So, P = V * (V / R) = V^2 / R