FPGAs run an order of magnitude slower than an ASIC would. Most of this is due to routing delays unless you take great care and do a lot of it semi-manually.

FPGAs run an order of magnitude slower than an ASIC would. Most of this is due to routing delays unless you take great care and do a lot of it semi-manually. On the logic side you can't easily do a lot of the fun stuff like cycle stealing and using latches because the FPGA toolchains don't handle that well.