> timing differences due to physical limitations of the hardware I see; so you're talking about step two as described here, do I have that right? https://en.w

> timing differences due to physical limitations of the hardware I see; so you're talking about step two as described here, do I have that right? https://en.wikipedia.org/wiki/Spectre_(security_vulnerability)#Detailed_explanation https://en.wikipedia.org/wiki/Spectre_(security_vulnerabilit... This seems like a failure of algorithm design to me, in the sense of not starting with a better model that more accurately encodes the possibility of timing attacks. That being the case it appears to me to be a problem still firmly residing in the domain of computer science. But, I'm a programmer, not a chip designer, and I have very little knowledge of this field, so I'm probably biased and not thinking about this correctly or with enough nuance.