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http://www.public.lyricsemiconductor.com/technology-gates.htm http://www.public.lyricsemiconductor.com/technology-gates.ht... This sounds fairly interesting. D

• Geee 16y ago
  Basically, they use lower voltage than is traditionally needed. Lowering the CMOS supply voltage turns the logic probabilistic due to thermal noise, and huge power savings are achieved when traded for some probability of error. Now, they can design their logic to tolerate the errors, or use the probabilistic logic to actually present random variables, where the output of the logic is a sample from the distribution.
  • sedachv 16y ago
    I did a little more digging and found these from the founder, Benjamin Vigoda: http://phm.cba.mit.edu/theses/03.07.vigoda.pdf http://phm.cba.mit.edu/theses/03.07.vigoda.pdf (PhD dissertation) http://webcache.googleusercontent.com/search?q=cache:hHev9gIgUy4J:cba.mit.edu/presentations/03.09.Vigoda.ppt+Ben+Vigoda&cd=5&hl=en&ct=clnk&gl=ca http://webcache.googleusercontent.com/search?q=cache:hHev9gI... (overview presentation) It seems that these chips are actually analog. Are the "soft gates" mentioned in the above a synonym for the effects of lowered CMOS voltage?