8 ms·
> exposing an MSR to flush the TLB, but only for recent CPUs You write to CR3 register to flush TLB (or use INVPCID to invalidate just a subset of TLB). So not
by vardump 9y ago
> exposing an MSR to flush the TLB, but only for recent CPUs
You write to CR3 register to flush TLB (or use INVPCID to invalidate just a subset of TLB). So not sure what that means, why would you need an MSR for that?
- sounds 9y agoI stand corrected, the MSR is to flush the branch prediction state. Updating my comment above.