8 ms·
Xerox Alto's 3 Mb/s Ethernet: Building a Gateway with a BeagleBone
- binhex 9y agoI love these types of posts. There is something really interesting about the detective work required to be able to talk to old devices like this.
- chrisweekly 9y agoAgreed! Meta for admins: shouldn't the headline include the year? (I've got comment downvote rights per karma > 500, but can't edit post headlines.)
- kens 9y agoWhy would the headline include the year? The article is from 2018.
- DannyB2 9y agoBYTE magazine, April 1980, page 115. NEW HIGH-SPEED COMMUNICATIONS BUS: Xerox Corporation recently made a public announcement of a new concept of processor-to-processor communications intended for an office environment. This novel concept is called "Ethernet", and is a result of some of the work being done in their research labs. In this concept, a single coaxial cable is used as a high-speed communications bus between all processors; communication protocol is handled through software or software supplemented by special-purpose hardware. Rumor has it that an Ethernet processor is now being developed by some form of joint arrangement between Xerox and Intel. http://www.americanradiohistory.com/Byte_Magazine.htm http://www.americanradiohistory.com/Byte_Magazine.htm https://archive.org/details/byte-magazine https://archive.org/details/byte-magazine
- ghostly_s 9y agoI've never considered networking as "processor-to-processor communications" before. Kind of an interesting angle.
- teh_klev 9y agoThe usage likely originates from the use of the word "processor" to mean a whole machine that does some kind of "processing", kinda like the IMP's (Interface Message Processor) on the early ARPANET. These days "processor" usually means a more narrow definition, i.e. just the CPU, rather than a whole machine.
- DannyB2 9y agoAh, but once upon a time, Long ago, in a galaxy far, far away, CPU meant a large metal enclosure with circuit boards, main memory, power supplies and cooling. Oh, and blinking lights. Don't forget the blinking lights like REAL computers on TV.
- godzillabrennus 9y agoFascinating to learn that the Ethernet design of the Alto influenced the design of TCP. This might be common knowledge to those who lived through that era but as a millennial I wasn’t aware of this.
- rbanffy 9y agoKid, you have no idea... ;-)
- kens 9y agoThe story is that the PARC engineers went to the TCP design meetings, but Xerox lawyers wouldn't let them say anything about Pup. So the PARC engineers would just ask questions until the TCP designers realized the flaws in their proposals: "Have you considered what would happen if..." And the TCP designers would go, "Hey! You've done this before, haven't you!"
- vvanders 9y agoThat's both an awesome anecdote and a great way to approach any design review. If you can take the time it's a great way provide technical feedback in a way that isn't hostile and keeps an open dialog.
- dfox 9y agoWhat is inside the Alto's ethernet transceiver? From the remark that interface between Alto and transceiver is TTL I gather that it is not same as 10M one (which transformer-coupled RS-422-ish differential interface) and also the collision signal detected by transceiver should probably be different.
- kens 9y agoThe transceiver basically has three parts. There's the logic side connected to the Alto, which XORs the sent data and received data to see if there's a collision. The cable-side circuitry has some analog stuff to put signals in and out of the coax. These two sides are connected via transformers for isolation. Finally there's a simple switching power supply to provide isolated 5.7V to the cable-side circuitry. (You want the Alto electrically isolated from the cable so you don't get ground loops and other nasty stuff from the cable.) The schematic for the transceiver is at: http://bitsavers.org/pdf/xerox/alto/schematics/209926B_Ethernet_Transceiver.pdf http://bitsavers.org/pdf/xerox/alto/schematics/209926B_Ether...
- CamperBob2 9y agoInteresting, I wonder what the funky magnetically-coupled circuit with Q1 and Q2 is for.
- kens 9y agoThat's the switching power supply for the circuitry on the coax side of isolation. The coils are coupled to E, F, G which feed the 5.7V power supply on the previous page.
- CamperBob2 9y agoThat's what I thought at first, but the pin numbers (5, 6, and 7) on the E/F/G windings at right overlap with the pin numbers for the primary, suggesting they're different parts altogether. Pretty confusing...
- rootbear 9y agoHere at NASA Goddard, old wiring is often never removed. In the cable trays in the hall outside my office is some ancient coaxial Ethernet cable. At one point, there is a tap and one of the standard cables that went from the tap to a workstation. I keep thinking I should grab the tap and squirrel it away as a historical artifact.
- mhalle 9y agoVampire tap. You had to place them at marked locations on the coax because of signal reflections.
- jacquesm 9y agoAnd because at that point the shield wires were spaced further apart so as not to short out the connection.
- jonsen 9y agoReally? Sounds like a major complication to the cable manufacturing process. Wouldn't all those holes in the shielding hose degrade cable specs? All for not having to drill a hole for the eventual connecting tap.
- jacquesm 9y agoIt is not that big a deal actually, either you drill a hole with a special tool and then align the tap with the center of the hole or, on some cable you align the tap with a special dot mark on the cable where the shield has been moved aside a couple of mm. It is a convenience at the slight cost of some loss. Far faster to connect to than drilling holes in insulation using yet another tool. It really adds up if you have to make a lot of drops on a cable. If there is one thing I am happy about then about then it is that we no longer have coax networks. Nightmare stuff. Flaky connections and weird voodoo problems.
- teh_klev 9y ago
- jonsen 9y agoHow did we make a similar adaptor in the 80'ies with a microprocessor running 2 MHz? Fortunately the PLA was invented. A few bits of memory and a little programmable logic. Enough to synchronize to the, in this case 2.35 MHz, Manchester coded bitstream and assemble the data bits into bytes. The processor was still not fast enough to handle the control bytes of the data stream in real time. It could actually handle the controlling logic, but then it had no time left for looping around. The trick was then to disable the processors address bus during program fetching and feed it instructions from a separate ROM, controlled by another small PLA which also handled the looping.
- bsder 9y agoWhile I love this (and I am ECSTATIC about the PRU documentation ... thankyouthankyouthankyouthankyouthankyouthankyouthankyou ... I have been using this right now), I would expect this would have been loads easier with even something really cheap like a MAX10 FPGA. However, he does mention needing a network stack, so maybe not.
- sigstoat 9y ago> I would expect this would have been loads easier with even something really cheap like a MAX10 FPGA. basically nothing is easier with an FPGA. faster, perhaps.
- bsder 9y agoIf I can draw a handful of gates, an FPGA eval board is almost ALWAYS easier. I can have a MAX10 evaluation board on my desk in less than 24 hours for probably less than Osh Park charged him. The real question is how much software is required. Once I have to start writing software or Verilog/VHDL, things slow down.
- kevin_thibedeau 9y ago> using a 74AHCT125 level shifter chip The 74x125 is not a level shifter. It is a tristate buffer that can be exploited for poor-man's level shifting with a suitable configuration of external components. It isn't an ideal part to do this and it would be nice if the purveyors of hacker/maker doodads didn't misrepresent what they're selling. > Without a resistor, the open-collector signal stayed at ground. Adding the resistors to my circuit fixed that problem. That never would have been an issue with an actual level shifter.
- stn8188 9y agoWhile you're technically correct, Nexperia outlines the technique for using the 74AHC series for level shifting here: https://assets.nexperia.com/documents/brochure/75017511.pdf https://assets.nexperia.com/documents/brochure/75017511.pdf.
- stephenjudkins 9y agoIt is explicitly advertised on Adafruit as a level shifter https://www.adafruit.com/product/1787 https://www.adafruit.com/product/1787
- thought_alarm 9y agoWhat makes ethernet "Ethernet"? There's 10BASE-T Ethernet, which is what we all use and has been around since the late 80s. There's 10BASE5 and 10BASE2 Ethernet, which uses a shared coax cable between machines and was around from the early-80s to the mid-90s. And then there's the pre-standard coax Ethernet that the Alto used in the 1970s. Is there a common technological thread between these three things, other than the name?
- fernly 9y agoI think the common thread is multiple sender/receivers on a single shared conductor using csma/cd. https://en.wikipedia.org/wiki/Carrier-sense_multiple_access_with_collision_detection https://en.wikipedia.org/wiki/Carrier-sense_multiple_access_...
- jweather 9y agoNot since 100Mbit... Gigabit is full duplex only and has no need for collision detection/avoidance.
- tyingq 9y agoSee token ring for shared conductor, but different coordination.[1]. There was a time when it wasn't clear which one would win out. [1] https://en.m.wikipedia.org/wiki/Token_ring https://en.m.wikipedia.org/wiki/Token_ring Edit: Also DecNet, SNA, Arcnet if you want some more view into competing ideas in the same time period.
- kijiki 9y agoAs you note, L1 has varied a bit, though the big change is that CSMA/CD has given way to essentially point to point L1 links with buffers and arbitration in the switches. The L2 header format has remained largely the same, with a few minor variants that can be automatically disambiguated.
- stevefan1999 9y agothis is so cool and nostalgic!