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ASID is not an instruction. It's basically an attribute in how MMU tables are set up. Processes usually get different ASIDs from each other and all their MMU pa
by puzzle 9y ago
ASID is not an instruction. It's basically an attribute in how MMU tables are set up. Processes usually get different ASIDs from each other and all their MMU pages are tagged with it.
- bogomipz 9y agoSorry I didn't mean instruction. It's the RISC equivalent attribute then?
- monocasa 9y agoIt's not a RISC/CISC thing. They're called ASIDs in AMD land as well.
- bogomipz 9y agoI guess I am confused was to why there is both an ASID and PCID for x86 then?
- monocasa 9y agoThey're Intel and AMD extensions respectively. They're tacked onto the virtualization extensions, and since every implementor (Xen, KVM, etc.) has just wrote separate backends for VT and SVM anyway, Intel and AMD haven't found the need to negotiate cross licensing.
- bogomipz 9y agoThank you this makes sense. Cheers
- puzzle 9y agoYes. There is still variety, though. On PowerPC, for example, there is the concept of segments. On 32bit systems, the address space is divided into 16 segments of 256MB each. Each of them has a privileged register that can be setup in different ways (e.g. half could be per-process, half machine-wide). The 4 bits from the segment ID eventually map to a 24 bit value (or trigger a protection violation if e.g. the page is kernel-only), so that the original 32bit address becomes a 32 - 4 + 24 = 52 bit virtual address. The MMU, then will look up the higher order bits in the address to convert from 52bit virtual addresses to actual 32bit physical addresses. The virtual address space is larger because in theory you could have processes with completely disjoint addressing (up to 1 million of 4GB each, i.e. 4PB). In the end, you still only have 32 bits to address memory chips, though. :-) On 64 bit systems, there are many more segments, 236. Instead of having (64 * billion) registers, there is a single register pointing to a hash table in memory that the CPU will walk through. Addresses are translated from 64->80->64 bits in a similar way.
- bogomipz 9y agoThanks, is your explanation all PowePC specific then?
- monocasa 9y agoThe individual MMU pages aren't tagged with ASIDs, it's more like you have N page table root pointers in hardware, and rather than saying "this is the current root pointer", you say "this is the root pointer for ASID N, and separate from that this is the current ASID".