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> >can actually combine x86 ISA instruction pairs into a micro-op > More complexity, and more tickets for the implementation bug lottery. Well, the slides (an
by jabl 9y ago
> >can actually combine x86 ISA instruction pairs into a micro-op
> More complexity, and more tickets for the implementation bug lottery.
Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.
- snvzz 9y agoIt does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence. Very nice and very clean when done as they propose with this RISC ISA.