This is a piece without substance since it basically says "Oh hey, competing chips actually selling to customers have some issues. We promise we'll be better wh

This is a piece without substance since it basically says "Oh hey, competing chips actually selling to customers have some issues. We promise we'll be better when our lab designs finally end up in your hands. Trust and fund us now!" We'll see. Anyone interested in what a better hardware/software-security architecture for RISC-V might look like should check out these exemplary projects: http://www.crash-safe.org/papers.html http://www.crash-safe.org/papers.html http://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ http://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://vtechworks.lib.vt.edu/bitstream/handle/10919/29244/edmison_joshua_dissertation.pdf?sequence=1&isAllowed=y https://vtechworks.lib.vt.edu/bitstream/handle/10919/29244/e... CHERI already runs FreeBSD on a FPGA machine. I previously suggested merging Rocket with a version of CHERI as a start for that reason. Then, Draper is modifying or has modified RISC-V to use SAFE architecture. They're creating a brand around it as below. http://www.draper.com/solution/inherently-secure-processor http://www.draper.com/solution/inherently-secure-processor So, that's what I've seen so far that addresses piles of vulnerabilities with a whole-system style of protection.