4 ms·

> there's a CISC->RISC translation layer... More like a mixture of something like CISC->VLIW and CISC->"micro-ops". Remember x86 implementations can actually c

> there's a CISC->RISC translation layer... More like a mixture of something like CISC->VLIW and CISC->"micro-ops". Remember x86 implementations can actually combine x86 ISA instruction pairs into a micro-op [0]. RISC is just a concept that was a great fit to the constraints the industry had in the nineties. It was great for achieving high clock speeds back then. The constraints are just different nowadays. [0]: https://en.wikichip.org/wiki/macro-operation_fusion https://en.wikichip.org/wiki/macro-operation_fusion

snvzz 9y ago
>VLIW In RISC-V parlance, it'd be the new vector extensions. They're pretty cool as they've made the width variable. Refer to 7th workshop proceedings. >micro-ops Are a fancy word. It just means a (hidden) RISC architecture. There's a bunch of RISC architectures out there, but they get down to doing more or less the same things. Most RISC and CISC architectures in use today are evolved from ones existing back in the 80s, and carry a lot of baggage. RISC-V benefits from having a clean slate at this, using the experience of existing ISAs. >can actually combine x86 ISA instruction pairs into a micro-op More complexity, and more tickets for the implementation bug lottery.
- jabl 9y ago
  > >can actually combine x86 ISA instruction pairs into a micro-op > More complexity, and more tickets for the implementation bug lottery. Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.
  - snvzz 9y ago
    It does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence. Very nice and very clean when done as they propose with this RISC ISA.