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Having complex instructions is not the only way to make a complex processor. With a very simple ISA, to even come close to what a modern processor can do with a

by fooker 9y ago

Having complex instructions is not the only way to make a complex processor. With a very simple ISA, to even come close to what a modern processor can do with a certain amount of time and power requires a ridiculously complicated design. This is why Spectre is as ubiquitous as it is. Speculative execution is not a feature someone implements just for the sake of it.

deleted 9y ago
[deleted]
snvzz 9y ago
>To even come close to what a modern processor can do with a certain amount of time and power REQUIRES a ridiculously complicated design. Requires is debatable. If someone manages to match it with a simpler design, it's an improvement. RISC-V open implementations are surprisingly very competitive already. >With a very simple ISA, Seems to imply that this is a minus, but what CISC really means in the present world is that there's a CISC->RISC translation layer, which is not free, and a lot of work passed down to toolchain developers, as they have to generate code for a CISC ISA. In x86/amd64, the complexity is such that no individual can be expected to understand the whole thing, and CPU designers, low level software and compiler developers have to deal with this (and will inevitably screw up). Why this isn't seen as a massive problem baffles me.
- vardump 9y ago
  > there's a CISC->RISC translation layer... More like a mixture of something like CISC->VLIW and CISC->"micro-ops". Remember x86 implementations can actually combine x86 ISA instruction pairs into a micro-op [0]. RISC is just a concept that was a great fit to the constraints the industry had in the nineties. It was great for achieving high clock speeds back then. The constraints are just different nowadays. [0]: https://en.wikichip.org/wiki/macro-operation_fusion https://en.wikichip.org/wiki/macro-operation_fusion
  - snvzz 9y ago
    >VLIW In RISC-V parlance, it'd be the new vector extensions. They're pretty cool as they've made the width variable. Refer to 7th workshop proceedings. >micro-ops Are a fancy word. It just means a (hidden) RISC architecture. There's a bunch of RISC architectures out there, but they get down to doing more or less the same things. Most RISC and CISC architectures in use today are evolved from ones existing back in the 80s, and carry a lot of baggage. RISC-V benefits from having a clean slate at this, using the experience of existing ISAs. >can actually combine x86 ISA instruction pairs into a micro-op More complexity, and more tickets for the implementation bug lottery.
    - jabl 9y ago
      > >can actually combine x86 ISA instruction pairs into a micro-op > More complexity, and more tickets for the implementation bug lottery. Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.
      - snvzz 9y ago
        It does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence. Very nice and very clean when done as they propose with this RISC ISA.
- fooker 9y ago
  >RISC-V open implementations are surprisingly very competitive already. Do you have some sources for this?

by fooker 9y ago

deleted 9y ago

[deleted]

snvzz 9y ago

>To even come close to what a modern processor can do with a certain amount of time and power REQUIRES a ridiculously complicated design. Requires is debatable. If someone manages to match it with a simpler design, it's an improvement. RISC-V open implementations are surprisingly very competitive already. >With a very simple ISA, Seems to imply that this is a minus, but what CISC really means in the present world is that there's a CISC->RISC translation layer, which is not free, and a lot of work passed down to toolchain developers, as they have to generate code for a CISC ISA. In x86/amd64, the complexity is such that no individual can be expected to understand the whole thing, and CPU designers, low level software and compiler developers have to deal with this (and will inevitably screw up). Why this isn't seen as a massive problem baffles me.

vardump 9y ago
> there's a CISC->RISC translation layer... More like a mixture of something like CISC->VLIW and CISC->"micro-ops". Remember x86 implementations can actually combine x86 ISA instruction pairs into a micro-op [0]. RISC is just a concept that was a great fit to the constraints the industry had in the nineties. It was great for achieving high clock speeds back then. The constraints are just different nowadays. [0]: https://en.wikichip.org/wiki/macro-operation_fusion https://en.wikichip.org/wiki/macro-operation_fusion
- snvzz 9y ago
  >VLIW In RISC-V parlance, it'd be the new vector extensions. They're pretty cool as they've made the width variable. Refer to 7th workshop proceedings. >micro-ops Are a fancy word. It just means a (hidden) RISC architecture. There's a bunch of RISC architectures out there, but they get down to doing more or less the same things. Most RISC and CISC architectures in use today are evolved from ones existing back in the 80s, and carry a lot of baggage. RISC-V benefits from having a clean slate at this, using the experience of existing ISAs. >can actually combine x86 ISA instruction pairs into a micro-op More complexity, and more tickets for the implementation bug lottery.
  - jabl 9y ago
    > >can actually combine x86 ISA instruction pairs into a micro-op > More complexity, and more tickets for the implementation bug lottery. Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.
    - snvzz 9y ago
      It does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence. Very nice and very clean when done as they propose with this RISC ISA.
fooker 9y ago
>RISC-V open implementations are surprisingly very competitive already. Do you have some sources for this?